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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Yen, Cheng-ChengSubject: search.filters.subject.ESD protection circuit

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Now showing 1 - 4 of 4
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    Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
    (2008-11-01)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mu m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
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    The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps
    (2009-06-01)
    Yen, Cheng-Cheng
    ;
    Ker, Ming-Dou
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-mu m CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a "latch-on" state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.
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    Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
    (2009-08-01)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18-mu m CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. The proposed on-chip transient-to-digital converter can be further combined with firmware cooperation to provide an effective solution to solve the system-level ESD protection issue in microelectronic systems equipped with CMOS ICs.
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    Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters
    (2008)
    Ker, Ming-Dou
    ;
    Liao, Chi-Sheng
    ;
    Yen, Cheng-Cheng
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance of detecting fast electrical transients has been verified in a 0.18-mu m CMOS integrated circuit (IC). The experimental results have confirmed that the proposed on-chip transient detection circuit can detect positive and negative fast electrical transients during system-level ESD zapping. Three board-level noise filtering networks have been investigated their enhancement on detection range of the proposed on-chip transient detection circuit. The chip-level solution can be further co-designed with the board-level solution in order to meet high system-level ESD specification.