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Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique
(2008-12-15)
Li, Yiming
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Li, Yih-Lang
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Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
In this work, we implement a Computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After Construction of RSMs. we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18 mu m CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
Electronic design automation using a unified optimization framework
(2008-12-15)
Li, Yiming
;
Yu, Shao-Ming
;
Li, Yih-Lang
;
資訊工程學系
;
電信工程研究所
This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential to perform optimization operations on various problems. The UOF provides basic interlaces to define a general problem and generic solver, enabling these two different research fields to be bridged. The components of the UOF can be separated into problem and solver components. These two parts work independently allowing high-level code to be reused, and rapidly adapted to new problems and solvers. The UOF is customized to deal with several optimization problems. The first experiment involves a well-known discrete combinational problem, wihle the second one studies the robustness for the reverse modeling problem, which is in high demanded by device manufacturing companies. Additionally, experiments are undertaken to determine the capability of the proposed methods in both analog and digital circuit design automation. The final experiment designs antenna for rapidly growing wireless communication. Most experiments are categorized as simulation-based optimization tasks in the microelectronics industry. The results confirm that UOF has excellent flexibility and extensibility to solve these problems successfully. The developed open-source project is publicly available. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
Preface
(2013-07-01)
Li, Yiming
;
Chen, Chun-Nan
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Kamakura, Yoshinari
;
McKenzie, Todd
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Shin, Mincheol
Temperature dependence on the contact size of GeSbTe films for phase change memories
(2008-09-01)
Li, Yiming
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Yu, Shao-Ming
;
Hwang, Chih-Hong
;
Kuo, Yi-Ting
;
資訊工程學系
In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater's aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater's thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.
A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors
(2004-10-01)
Li, Yiming
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
;
友訊交大聯合研發中心
A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I-D - V-G, I-D - V-D, transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.
A Quantum Correction Model for Nanoscale Double-Gate MOS Devices Under Inversion Conditions
(2003-12-01)
Li, Yiming
;
Tang, Ting-Wei
;
Yu, Shao-Ming
;
資訊工程學系
;
友訊交大聯合研發中心
A quantum correction model for nanoscale double-gate MOSFETs under inversion conditions is proposed. Based on the solution of Schrodinger-Poisson equations, the developed quantum correction model is optimized with respect to (i) the left and right positions of the charge concentration peak, (ii) the maximum of the charge concentration, (iii) the total inversion charge sheet density, and (iv) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses, silicon film thicknesses, and applied voltages. Compared to the Schrodinger-Poisson results, our model prediction is within 3.0% of accuracy. This quantum correction model has continuous derivatives and is therefore amenable to a device simulator.
Intelligent optical proximity correction using genetic algorithm with model- and rule-based approaches
(2009-03-01)
Li, Yiming
;
Yu, Shao-Ming
;
Li, Yih-Lang
;
資訊工程學系
;
電信工程研究所
Optical lithography is one of the key technologies in semiconductor material and device fabrications. It is a process to transfer the layouts of desired pattern onto the wafers. However, the exposure on wafer has distortions due to the proximity effects. As the minimum feature sizes of explored samples continue to shrink, the mismatch between the pattern and the experimental result on wafer is significant. Corrections of mask patterns between the sample and post exposure result are thus necessary. Optical proximity correction (OPC) is the process of modifying the geometries of the layouts to compensate for the non-ideal properties of the lithography process. Given the shapes desired on the wafer, the mask is modified to improve the reproduction of the critical geometry. In this work, we propose an intelligent OPC technique for process distortion compensation of layout mask. To perform the mask correction in sub-wavelength era, two different strategies including the genetic algorithm (GA) with model-based OPC and the GA with rule-based OPC methods are examined. The proposed intelligent system consists of three parts: the preprocess, the OPC engine, and the post-process. During the pre-process, the pattern analyzer will analysis all patterns and then divided them into many segments for model-based OPC or generates assistant patterns for rule-based OPC. Secondly, the OPC module is applied to correct the mask. The intelligent module searches the whole problem domain to find out the best combination of the mask shape by the GA. The corrected mask is verified by performing lithographic simulation to get the error norm between exposed result and desired layout. Finally, the mask verification is conducted in the post-process. By testing on several fundamental patterns, this approach shows good correction accuracy and efficiency, compared with experimentally fabricated samples. It can be applied to perform the mask correction in sub-wavelength era. (C) 2008 Elsevier B.V. All rights reserved.
Discrete dopant fluctuated 20nm/15nm-gate planar CMOS
(2007)
Yang, Fu-Liang
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Hwang, Jiunn-Ren
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Chen, Hung-Ming
;
Shen, Jeng-Jung
;
Yu, Shao-Ming
We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V-t standard deviation up to 40mV for 20nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V-t variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors
(2006-09-01)
Li, Yiming
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
;
Department of Computer Science
In this study, we explore random-dopant-induced threshold voltage fluctuation by solving a quantum correction model. Fluctuation of the threshold voltage for three nanoscale transistors, single-, double-, and surrounding-gate (SG, DG, and AG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are computationally compared. To calculate the variance of the threshold voltages of the SG, DG, and AG MOSFETs, a quantum correction model under equilibrium conditions is expanded and numerically solved using perturbation and monotone iterative methods. Fluctuation of the threshold voltage resulting from the random dopant, gate oxide thickness, channel film thickness, gate channel length, and device width are calculated for the three devices. Quantum mechanical and classical results give similar predictions for fluctuation of the threshold voltage with respect to different parameters including the dimensions of the device and the channel doping. Fluctuation increases when the channel doping concentration, channel film thickness, and gate oxide thickness increase, On the other hand, it decreases when the channel length and device width increase. Calculation results of the quantum correction model are quantitatively higher than those of classical estimation in accordance with different quantum confinement effects in nanoscale SG, DG, and AG MOSFETs. It is found that the AG MOSFET has the smallest threshold voltage fluctuation among the three device structures due to its good channel controllability. In contrast to the conventional quantum Monte Carlo approach and the small-signal analysis of the Schrodinger-Poisson equations, this computationally cost-effective quantum correction approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
Strained CMOS devices with shallow-trench-isolation stress buffer layers
(2008-04-01)
Li, Yiming
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Chen, Hung-Ming
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Yu, Shao-Ming
;
Hwang, Jiunn-Ren
;
Yang, Fu-Liang
In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.

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