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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Yu, Shao-MingSubject: search.filters.subject.FinFET

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Now showing 1 - 3 of 3
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    Discrete Dopant Induced Electrical and Thermal Fluctuation in Nanoscale SOI FinFET
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    Huang, Hsuan-Ming
    ;
    電信工程研究所
    The International Roadmap for Semiconductors has forecasted a transition from conventional bulk device to silicon-on-insulator (SOI) one, and then to multiple-gate SOI for high-performance devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, the discrete dopant induced electrical and thermal fluctuation of 16nm SOI FinFETs is for the first time explored. A three-dimensional atomistic" device simulation with quantum hydrodynamic equation is proposed and performed for electrical and thermal characteristics of the discrete dopant fluctuated SOI FinFETs. Discrete dopants are statistically positioned in the 3D channel region to study associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Effect of the discrete-dopant-number- and discrete-dopant-position-induced fluctuations on device characteristic including variations of the lattice and electron temperatures are advanced. The large-scale computational statistics study provides us an insight into the fluctuation of electrical and thermal characteristics and mechanism of immunity against fluctuation in SOI FinFETs.
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    Three-dimensional simulation of random-dopant-induced threshold voltage fluctuation in nanoscale Fin-typed field effect transistors
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    Huang, Hsuan-Ming
    ;
    資訊工程學系
    Nanoscale multiple-gate fin-typed field effect transistors (FinFETs) are promising candidates for next generation semiconductor devices. Impact of the discrete-dopant number and discrete-dopant position on device characteristics is crucial for nanoscale semiconductor devices. In this paper, we study the discrete-dopant-induced potential and threshold voltage fluctuations in 16nm triple-gate FinFET devices. Discrete dopants are statistically positioned into the three dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". It is found that the inhomogeneity of the potential induced by the discreteness of the channel dopants significantly disturbs device threshold voltage, and thus the device characteristics. This study provides an insight into the source of fluctuation and fluctuations induced by discrete dopants in ultra-small field effect transistors with vertical channel structures.
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    Item type:Item,
    Numerical simulation of static noise margin for a six-transistor static random access memory cell with 32nm fin-typed field effect transistors
    (2007)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yu, Shao-Ming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (sigma-(S N M)) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower sigma-(S N M). Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.