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Author: search.filters.author.Yu, Shao-MingSubject: search.filters.subject.simulation

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Now showing 1 - 3 of 3
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    Strained CMOS devices with shallow-trench-isolation stress buffer layers
    (2008-04-01)
    Li, Yiming
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    Chen, Hung-Ming
    ;
    Yu, Shao-Ming
    ;
    Hwang, Jiunn-Ren
    ;
    Yang, Fu-Liang
    In this brief, shallow-trench-isolation (STI) stress buffer techniques, including sidewall stress buffer and channel surface buffer layers, are developed to reduce the impact of compressive STI stress on the mobility of advanced n-type MOS (NMOS) devices. Our investigation shows that a 7% driving current gain at an NMOS device has been achieved, whereas no degradation at a p-type MOS (PMOS) device was observed. The same junction leakage at both the NMOS and PMOS devices was maintained. A stress relaxation model with simulation is thus proposed to account for the enhanced transport characteristics.
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    An optimal silicidation technique for electrostatic discharge protection sub-100 nm CMOS devices in VLSI circuit
    (2007-02-01)
    Yu, Shao-Ming
    ;
    Lee, Jam-Wen
    ;
    Li, Yiming
    ;
    資訊工程學系
    ;
    電信工程研究所
    In this paper we propose a silicide design consideration for electrostatic discharge (ESD) protection in nanoscale CMOS devices. According to our practical implementation, it is found that a comprehensive silicide optimization can be achieved on the gate, drain, and source sides with very few testkey designs. Our study shows that there is a high characteristic efficiency for various conditions in particular, for optimizing the performance of sub-100 nm complementary metal-oxide-semiconductor devices in system-on-a-chip era. (c) 2006 Elsevier B.V. All rights reserved.
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    A coupled-simulation-and-optimization approach to nanodevice fabrication with minimization of electrical characteristics fluctuation
    (2007-11-01)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    資訊工程學系
    ;
    電信工程研究所
    ;
    Department of Computer Science
    In this paper, a simulation-based optimization methodology for nanoscale complementary metal-oxide-semiconductor (CMOS) device fabrication is advanced. Fluctuation of electrical characteristics is simultaneously considered and minimized in the optimization procedure. Integration of device and process simulation is implemented to evaluate device performances, where the hybrid intelligent approach enables us to extract optimal recipes which are subject to targeted device specification. Production of CMOS devices now enters the technology node of 65 nm; therefore, random-dopant-induced characteristic fluctuation should be minimized when a set of fabrication parameters is suggested. Verification of the optimization methodology is tested and performed for the 65-nm CMOS device. Compared with realistic fabricated and measured data, this approach can achieve the device characteristics; e.g., for the explored 65-nm n-type MOS field effect transistor, the on-state current > 0.35 mA/mu m, the off-state current < 1.5e - 11 A/mu m, and the threshold voltage = 0.43 V. Meanwhile, it reduces the threshold voltage fluctuation (sigma(vth) similar to 0.017 V). This approach provides an alternative to accelerate the tuning of process parameters and benefits manufacturing of nanoscale CMOS devices.