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Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique
(2008-12-15)
Li, Yiming
;
Li, Yih-Lang
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
In this work, we implement a Computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After Construction of RSMs. we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18 mu m CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
Electronic design automation using a unified optimization framework
(2008-12-15)
Li, Yiming
;
Yu, Shao-Ming
;
Li, Yih-Lang
;
資訊工程學系
;
電信工程研究所
This work proposes an object-oriented unified optimization framework (UOF) for general problem optimization. Based on biological inspired techniques, numerical deterministic methods, and C++ objective design, the UOF itself has significant potential to perform optimization operations on various problems. The UOF provides basic interlaces to define a general problem and generic solver, enabling these two different research fields to be bridged. The components of the UOF can be separated into problem and solver components. These two parts work independently allowing high-level code to be reused, and rapidly adapted to new problems and solvers. The UOF is customized to deal with several optimization problems. The first experiment involves a well-known discrete combinational problem, wihle the second one studies the robustness for the reverse modeling problem, which is in high demanded by device manufacturing companies. Additionally, experiments are undertaken to determine the capability of the proposed methods in both analog and digital circuit design automation. The final experiment designs antenna for rapidly growing wireless communication. Most experiments are categorized as simulation-based optimization tasks in the microelectronics industry. The results confirm that UOF has excellent flexibility and extensibility to solve these problems successfully. The developed open-source project is publicly available. (C) 2007 IMACS. Published by Elsevier B.V. All rights reserved.
A compact model for electrostatic discharge protection nanoelectronics simulation
(2005)
Chou, Hung-Mu
;
Yu, Shao-Ming
;
Lee, Jam-Wem
;
Li, Yiming
;
電信工程研究所
In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.
A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation
(2006-07-01)
Li, Yiming
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
;
Department of Computer Science
In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
Preface
(2013-07-01)
Li, Yiming
;
Chen, Chun-Nan
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Kamakura, Yoshinari
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McKenzie, Todd
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Shin, Mincheol
Temperature dependence on the contact size of GeSbTe films for phase change memories
(2008-09-01)
Li, Yiming
;
Yu, Shao-Ming
;
Hwang, Chih-Hong
;
Kuo, Yi-Ting
;
資訊工程學系
In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater's aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater's thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.
A Novel Approach to Compact Model Parameter Extraction for Excimer Laser Annealed Complementary Thin Film Transistors
(2004-10-01)
Li, Yiming
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
;
友訊交大聯合研發中心
A unified physical-based model parameter extraction technique for excimer laser annealed lower temperature polycrystalline silicon (LTPS) complementary thin film transistors (TFTs) is for the first time proposed. For two well-known compact models of LTPS TFT, Rensselaer Polytechnic Institute (RPI) V1 and V2 models, our approach sequentially optimizes the model parameters in the regions of linear, subthreshold, saturation, and leakage. Compared with the measured results, the extracted I-D - V-G, I-D - V-D, transconductance, and output conductance are within 3% of accuracy. The agreement with the experimental data is excellent for the n- and p-type LTPS TFTs with different length and width. This extraction technique bridges the fabrication of LTPS TFTs and the design of complementary system on panel circuits.
A Quantum Correction Model for Nanoscale Double-Gate MOS Devices Under Inversion Conditions
(2003-12-01)
Li, Yiming
;
Tang, Ting-Wei
;
Yu, Shao-Ming
;
資訊工程學系
;
友訊交大聯合研發中心
A quantum correction model for nanoscale double-gate MOSFETs under inversion conditions is proposed. Based on the solution of Schrodinger-Poisson equations, the developed quantum correction model is optimized with respect to (i) the left and right positions of the charge concentration peak, (ii) the maximum of the charge concentration, (iii) the total inversion charge sheet density, and (iv) the average inversion charge depth, respectively. This model can predict inversion layer electron density for various oxide thicknesses, silicon film thicknesses, and applied voltages. Compared to the Schrodinger-Poisson results, our model prediction is within 3.0% of accuracy. This quantum correction model has continuous derivatives and is therefore amenable to a device simulator.
Monotone iterative method for numerical solution of nonlinear ODEs in MOSFET RF circuit simulation
(2005)
Li, Yiming
;
Yu, Shao-Ming
;
Wang, Chuan-Sheng
;
電信工程研究所
;
Institute of Communications Engineering
(MOSFET) radio frequency (RF) circuit as a system of nonlinear ordinary differential equations. Then we solve them with the waveform relaxation method, the monotone iterative method, and Runge-Kutta method directly in time domain. With the monotone iterative method, we prove each decoupled and transformed circuit equation converges monotonically. In comparison with the HSPICE outputs, results calculated with our method are stable and robust in both the time and frequency domains. Convergence properties for the monotone iterative and outer iterative loops axe also presented and discussed. This method provides an alternative in the time domain numerical solution of MOSFET RF circuit equations.
Parallel simulation of deep sub-micron double-gate metal-oxide-semiconductor field effect transistors
(2005)
Yu, Shao-Ming
;
Chou, Hung-Mu
;
Lo, Shih-Ching
;
資訊工程學系
;
Department of Computer Science
Drift-Diffusion Density Gradient model (DD-DG) is the most popular model for simulating carrier transport phenomena in sub-micron semiconductor device, especially in two- or three-dimensional space. In deep sub-micron regime, the width effects cannot be neglected while simulating, i.e., three-dimensional simulation must be considered. However, three-dimensional computing is time-consuming. Fortunately, the dilemma of time consuming or rough approximation can be overcame by advanced computing technique. In this paper, we employ a parallel direct solving method to simulate double-gate metal-oxide-semiconductor field effect transistors (DG-MOSFET). The computational benchmarks of the parallel simulation, parallel speedup, load balance, and efficiency are studied in this work. Parallel numerical simulation of semiconductor devices is shown to be an indispensable tool for fast characterization and optimal design of semiconductor devices.

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