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Author: search.filters.author.Zan, HW

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Now showing 1 - 10 of 17
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    Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors
    (2000-07-01)
    Shih, PS
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    Zan, HW
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    Chang, TC
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    Huang, TY
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    Chang, CY
    N-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.
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    Dimensional effects on the reliability of polycrystalline silicon thin-film transistors
    (2000-08-01)
    Zan, HW
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    Shih, PS
    ;
    Chang, TC
    ;
    Chang, CY
    ;
    電子工程學系及電子研究所
    We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I-min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated SI-H bonds. (C) 2000 Elsevier Science Ltd. All rights reserved.
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    Reliability of laser-activated low-temperature polycrystalline silicon thin-film transistors
    (2002-06-24)
    Peng, DZ
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    Chang, TC
    ;
    Zan, HW
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    Huang, TY
    ;
    Chang, CY
    In this letter, the characteristics and reliability of laser-activated polycrystalline silicon thin-film transistors (poly-Si TFTs) have been investigated by stressing the devices under V-ds=12 V and V-gs=15 V. In comparison with traditional furnace-activated poly-Si TFTs, the leakage current is relatively large for laser-activated poly-Si TFTs. Further, while the degradation rates of threshold voltage and subthreshold swing are comparable to those of traditional furnace-activated TFTs, the post-stress leakage and on/off current ratio for laser-activated poly-Si TFTs degrade much faster than those of furnace-activated counterparts. The laser activation modifies the grain structure between the drain and the channel region, and causes grain discontinuity extending from the drain to the channel region. As a result, an inferior reliability with extra trap state density and larger leakage current was observed in the laser-activated poly-Si TFTs. (C) 2002 American Institute of Physics.
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    Comparison of poly-Si films deposited by UHVCVD and LPCVD and its application for thin film transistors
    (2002-09-26)
    Peng, DZ
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    Zan, HW
    ;
    Shih, PS
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    Chang, TC
    ;
    Lin, CW
    The ultra-high vacuum chemical vapor deposition (UHVCVD) system can deposit poly-Si film without any laser or furnace annealing. The uniformity of threshold voltage and mobility is superior to that deposited by low-pressure chemical vapor deposition (LPCVD) system. However, due to the deposition in polycrystalline phase for UHVCVD, the film surface is rough and results in low field effect mobility compared to that obtained by LPCVD using disilane (Si2H6) in amorphous phase followed by solid phase crystallization (SPC). The on-off current ratio for UHVCVD deposited poly-Si thin film transistors (TFTs) is approximately one order smaller, however, the leakage current for LPCVD SPC TFTs is higher. In this experiment, NH3 was introduced to both of the two samples to improve the device performance. It can be shown that improvements on device characteristics are more significant for UHVCVD deposited poly-Si TFTs, e.g. threshold voltage decreased dramatically and the on-off current ratio improved by two orders of magnitude. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    A W-spacer GOLD TFT with high performance and high reliability
    (2002-09-26)
    Zan, HW
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    Peng, DZ
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    Shih, PS
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    Chang, TC
    ;
    Liu, PT
    In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    Polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain
    (2002-12-16)
    Peng, DZ
    ;
    Chang, TC
    ;
    Shih, PS
    ;
    Zan, HW
    ;
    Huang, TY
    We have fabricated a polycrystalline silicon thin-film transistor with self-aligned SiGe raised source/drain (SiGe-RSD TFT). The SiGe-RSD regions were grown selectively by ultrahigh vacuum chemical vapor deposition at 550 degreesC. It was observed that, with SiH4 and GeH4 gas flow rates of 5 and 2 sccm, respectively, the poly-SiGe could be selectively grown up to 100 nm for source/drain regions. The resultant transistor structure features an ultrathin active channel region (20 nm) and a self-aligned thick source/drain region (120 nm), which is ideally suited for optimum performance. The significant improvements in electrical characteristics, such as higher turn-on current, lower leakage current, and higher drain breakdown voltage have been observed in the SiGe-RSD TFT, compared to the conventional TFT counterpart. These results indicate that TFTs with SiGe raised source/drain structure would be highly promising for ultrathin TFTs applications. (C) 2002 American Institute of Physics.
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    Analysis of narrow width effects in polycrystalline silicon thin film transistors
    (2003-01-01)
    Zan, HW
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    Chang, TC
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    Shih, PS
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    Peng, DZ
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    Huang, TY
    In this study, narrow width effects of polycrystalline silicon thin film transistors (poly-Si TFTs) are investigated. With reducing channel width, TFT characteristics such as. mobility, threshold voltage, and subthreshold swing are found to improve dramatically. To gain insight on the origin of the narrow width effects, a physically-based model is proposed to simulate the output characteristics of poly-Si TFTs. Excellent fitting with the experimental data is observed over a wide range of drain bias, gate bias, and channel width. Our model shows that both the deep state density and-tail state density are reduced with reducing channel width, thus accounting for the improved TFT characteristics. In addition, subthreshold swings of poly-Si TFTs with various channel widths and lengths are compared. It is found that the subthreshold swings of poly-Si TFTs with the same channel area are identical, indicating that the grain-boundary trap density is reduced due to the reduction of channel area.
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    A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain
    (2003-08-01)
    Zan, HW
    ;
    Chang, TC
    ;
    Shih, PS
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    Peng, DZ
    ;
    Kuo, PY
    With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.
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    Short-channel poly-Si thin-film transistors with ultrathin channel and self-aligned tungsten-clad source/drain
    (2004)
    Zan, HW
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    Chang, TC
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    Shih, PS
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    Peng, DZ
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    Kuo, PY
    A short-channel polycrystalline silicon (poly-Si) thin-film transistor (W/L=10 mum/3 mum) with an ultrathin channel (30 nm) and self-aligned tungsten-clad source/drain structure is demonstrated. With WF6 and SiH4 gas flow ratio of 40/12, selectively deposited tungsten film over 100 nm thick can be easily grown on source/drain regions. As a result, the parasitic source/drain resistance is greatly reduced, leading to improvement of device driving ability. Because tungsten deposition can be carried out at a low processing temperature of 300degreesC, the proposed simple structure is compatible with conventional top-gate structure and can be readily applied to low-temperature poly-Si fabrication. (C) 2003 The Electrochemical Society.
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    High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure
    (2004-05-10)
    Wu, YC
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    Chang, TC
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    Chang, CY
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    Chen, CS
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    Tu, CH
    This investigation examines polycrystalline silicon thin-film transistors (TFTs) with multiple nanowire channels and a lightly doped drain (LDD). A device with an LDD structure exhibits low leakage current because the lateral electrical field is reduced in the drain offset region. Additionally, multiple nanowire channels can generate fewer defects in the polysilicon grain boundary and have more efficient NH3 plasma passivation than single-channel TFTs, further reducing leakage current. They exhibit superior electrical characteristics to those of single-channel TFTs, such as a higher ON/OFF current ratio (>10(8)), a better subthreshold slope of 110 mV/decade, an absence of drain-induced barrier lowering, and suppressed kink-effect. Devices with the proposed TFTs are highly promising for use in active-matrix liquid-crystal display technologies. (C) 2004 American Institute of Physics.