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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

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Essential factors that affect bioelectricity generation byRhodopseudomonas palustrisstrainPS3in paddy soil microbial fuel cells
(1970-01-01)
Liu, Chia-Hung
;
Lee, Sook-Kuan
;
Ou, I-Che
;
Tsai, Kun-Ju
;
Lee, Yu
A plant-associated phototrophic bacterium,R. palustrisstrain PS3, was inoculated into a soil-based MFC to generate electricity. We evaluated the performance of this soil-based microbial fuel cell (MFC) and elucidated the essential factors that contributed to power generation. PS3 showed the potential to enhance power generation, especially when the apparatus was operated in a sealed chamber with illumination.We deduced that the improved power performance was due to the enhanced electron transport through the living electrode that was grown as a PS3 biofilm via photoheterotrophic metabolism. In addition, we suggested that the interplay between phototrophic fixation of ambient CO(2)and anaerobic oxidation of ferrous iron in soil was also involved in the increased power output. We implemented CMOS (complementary metal-oxide-semiconductor) technology with the soil-based MFC to harvest energy in a more efficient and stable manner. The above system is expected to provide a potentially low-cost and low-energy system with a high power conversion efficiency for practical applications in the future.
A high-speed 850-nm optical receiver by integrating Si photodiode and CMOS IC
(2008-01-01)
Hsin, Y. M.
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Huang, W. K.
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Liu, Y. C.
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Yan, B. E.
;
Chen, W. Z.
In this work, three approaches are proposed to implement high-speed 850-nm optical receivers fully in standard bulk 0.18 pm silicon (Si) CMOS technology. In the first approach, the lateral p-i-n photodiode (PD) with designed block well to limit the photocarriers being generated from the laterally depleted regions is integrated in optical receiver. The receiver consists of TIA, LA, offset-cancellation-network and buffer to provide a conversion gain of 110 dB Omega and data rate of 2.5 Gbps operation. In the second receiver, the spatially modulated PD (SMPD) with -3 dB bandwidth of 590 MHz is integrated in optical receiver with the extra adaptive equalizer and demonstrates a data rate of 3.125 Gbps. Finally, the proposed novel structure of PD eliminates the slow diffusion photocarriers by using body contact design to create a new current path under the PD. A bandwidth of 2.8 GHz with 100 % improvement in PD is obtained. The eye diagrams of PD with cable connected amplifiers at 2.5 Gbps, 4 Gbps and 5 Gbps are demonstrated. Furthermore, the optical receiver's optical-electrical (O-E) conversion bandwidth is also increased from 3.6 GHz to 4.3 GHz. To our knowledge, these are the highest O-E conversion bandwidth of the PD and optical receiver ever reported by using the standard bulk 0.18 mu m Si CMOS technology.
A Low Phase Noise CMOS Voltage-Controlled SAW Oscillator for OC-192 Applications
(2007-01-01)
Lin, Jon-Hong
;
Kang, Nai-Yuan
;
Kao, Yao-Huang
;
電信工程研究所
;
Institute of Communications Engineering
A surface acoustic wave (SAW) resonator based oscillator was developed in response to OC-192 applications. The effects of parasitic capacitance were investigated. This oscillator was fabricated by tsmc 0.18 mu m CMOS process. The oscillator's white phase noise floor is -175 dBc/Hz for carrier offset frequency greater than 1 MHz and -136 dBc/Hz at 10 kHz carrier offset. The oscillator provides 4.0 dBm of output power and consumes 15mA from +1.2V DC power supply.
Modeling and suppressing substrate coupling of RF CMOS FMCW sensor incorporating synthetic quasi-TEM transmission lines
(2007)
Wang, Sen
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Wu, Hsien-Shun
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Chang, Chi-Ho
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Tzuang, Ching-Kuang C.
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電信工程研究所
An electromagnetic (EM) model for investigating the substrate coupling of the CMOS FMCW sensor is presented. Such EM model, which invokes the large-scale field analyses, can make a quantitative assessment of the EM coupling and can be applied into the system simulations for designing the CMOS FMCW sensor. A practical example is reported to demonstrate the feasibility of the proposed model. Furthermore, the model is applied to validate the effectiveness of the chip-scale leakage suppression by incorporating the complementary conducting strips transmission line (CCS-TL). The system simulations, which are performed with the proposed EM model, compared with those of the experimental results, showing a slight difference of 2.6dB on the prediction of the isolation improvement.
A CMOS miniaturized C-band active bandpass filter
(2006)
Tzuang, Ching-Kuang C.
;
Wu, Hsine-Hung
;
Wu, Hsien-Shun
;
Chen, Johnsea
;
電信工程研究所
This paper presents a novel topology of the CMOS active bandpass filter (BPF) at C-band. The parallel resonators in the BPF are realized by the monolithic synthetic quasi-TEM transmission line (TL), the so-called complementary conducting strip transmission line (CCS-TL). The characteristics of the CMOS monolithic CCS-TL are investigated by a series of experiments. The characteristics of the CCS-TL, including the characteristic impedance, phase constant, and attenuation constant, are extracted from the measured two-port scattering parameters for the filter design. The loss of the CCS-TL resonators is reduced by integrating an active network A practical example of a second-order active BPF is designed and fabricated by using a typical 0.18 mu m CMOS 1P6M technology. The size of prototype is 1.23 mm by 0.88 mm. The measured results show the following characteristics. The center frequency of the proposed active BPF is 6.02 GHz. The bandwidth is 1.26 GHz, and the return-loss, which is measured based on 50 Omega-system, is -7.5 dB. The insertion-loss of the BPF is 2.2dB when the BPF draws 3.0mA from a +1.8V power supply.
A low-power current-reuse LNA for ultra-wideband wireless receivers from 3.1 to 10.6 GHz
(2007)
Kao, H. L.
;
Chin, Albert
;
Chang, K. C.
;
McAlister, S. P.
;
交大名義發表
We present an ultra-wideband 3.1-10.6 GHz low-noise amplifier which uses a two-stage current-reuse structure to reduce the power. Fabricated in a 0.18 mu m CMOS process, the IC prototype achieved a power gain of 9.3 dB, a noise figure (NF) of < 5.6 dB, an input match of < -8 dB over the band, while consuming only 9.4 mW.
奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫三：奈米CMOS技術之60∼110-GHz射頻前端關鍵性積體電路之研究與設計
(2008)
胡樹一
;
Hu Shu-I
;
國立交通大學電子工程學系及電子研究所
應用於傳遞高品質視訊影像的家用無線網路在不久的將來將變的普及，高速以及高資料量的傳送，將使區域性的寬頻無線通訊系統的需求更為提高。因此，如何設計應用於更高操作頻段的無線傳輸系統，如60~110-GHz 之V-Band 與W-Band 之區域性無線通訊系統，將是一個重要的研究主題。隨著CMOS 製程由深次微米(deep submicron)進步到奈米(nanometer)，電晶體的最高操作頻率(ft)已超過100GHz，使用奈米CMOS 製程，設計操作頻率在60~110-GHz 之 V-Band 與W-Band 的射頻積體電路已經可望實現。本計畫將以130nm ~ 45nm之奈米CMOS技術來研究並設計操作頻率在60~110-GHz 的高頻段無線通訊收發器之前端主要電路元件。首先將以130-nm 與90-nm CMOS 製程技術，設計操作頻率於60 GHz 的V-Band 射頻前端接收器與發射器電路；延續設計 60-GHz 頻段之前端電路的知識，設計應用於W-Band 頻帶之窄頻與寬頻之射頻前端接收器與發射器之主要關鍵電路。此外，本計畫也將針對所設計的V-Band 與W-Band 射頻關鍵性電路進行低功率以及高性能的改善，使電路在高頻操作下具有高性能外，亦能具有低電壓低功率消耗的特性。此外，亦將進行前瞻性研究，以創新的觀念設計電路，期望能將各主要的前端電路元件之性能推至極限。預計完成的主要前端電路元件有：低雜訊放大器、混波器、震盪器、除頻器以及功率放大器；各元件的功能及設計考量簡述如下: 1. 低雜訊放大器 (Low-Noise Amplifier)：低雜訊放大器的目的在於提供足夠的增益以及低的雜訊指數(NF)，以降低後級電路對雜訊的影響，對整個系統的靈敏度有決定性的影響。此計畫除了針對雜訊指數的特性改善外，也將設計使其有較低的功率消耗。 2. 混波器 (Mixer)：混波器目的在將射頻訊號與本地震盪訊號相乘，使訊號頻率降至中頻或基頻；或將中頻或基頻訊號與本地振盪訊號相乘，使訊號升至為射頻訊號。設計上為了使系統的動態範圍提高，混波器需有足夠的線性度(linearity)，以提高動態區間(dynamic range)。 3. 震盪器(VCO)：震盪器目的是產生本地震盪訊號，提供混波器將訊號進行升降頻使用。設計上，震盪器需要有好的相位雜訊(phase noise)，高頻率調整範圍，以及低功率的特性。 4. 除頻器(Frequency Divider) 高頻除頻器為頻率合成器中的一個重要元件，此電路將震盪器的輸出頻率先行除頻，以使後端的電路處理較為低頻率的訊號，進而降低整體的功率消耗。此高頻除頻器在設計上，要能處理寬頻的輸入訊號，同時低功率消耗也是重要的考量。 5. 功率放大器 (Power Amplifier)：功率放大器的目的在將射頻訊號放大並驅動天線將訊號發射出去，為使訊號在傳遞時減少失真，以及降低功率消耗，功率放大器需有優良的功率效益以及好的線性度。在實現及量測驗證過此計畫中之各元件的功能後，將進一步與其他子計畫成果整合，以應用於無線通訊之收發器系統，並同時改善各電路元件的特性。預計此三年期間完成多個主要關鍵性的電路方塊，以運用於未來的57~64-GHz 頻段以及75~110-GHz 之無線通訊傳送接收機與傳送機之使用；同時，本三年型研究計畫也將整合已開發的 60-GHz 頻段之關鍵性主要電路，並實現57~64-GHz 之V-Band 寬頻無線通訊系統，並將此系統實際地應用在高速高資料量的訊息傳輸上。
金屬閘極及高介電係數介電質材料在奈米電子元件的應用
(2008)
荊鳳德
;
CHIN ALBERT
;
國立交通大學電子工程學系及電子研究所
缺乏適當的金屬功函數當作閘極電極（Metal gate）和費米能階拴鎖效應（Fermi-level pinning）是金屬與高介電係數介電質材料應用在矽奈米-互補式金氧半場效電晶體元件上兩個最主要的問題。尤其，製作p 型金屬閘極/高介電係數介電質金氧半場效電晶體更是特別的困難。其原因為在所有元素週期表中，只有銥金屬（Ir：功函數為5.27eV）和鉑（Pt：功函數為5.65eV）之功函數值是高於被要求的5.2eV。雖然飛思卡爾公司（Freescale Semiconductor）已經發表了使用碳化鉭材料當作金屬閘極電極並獲得良好的n 型金氧半場效電晶體特性，但是開發其他具低功函數的金屬或金屬氮化物（MN）材料仍然是需要的。這是因為金屬與氮（M-N）的鍵結能普遍比金屬碳化物中金屬和碳（M-C）的鍵結能高而具有較穩定的特性。本計畫主持人-荊鳳德教授近年來在雙功函數金屬閘極互補式金氧半電晶體之研究（發表於2003 年IEDM）與高功函數氧化銥閘極在互補式金氧半電晶體之研究(分別發表於2004 年IEDM 及2005 年VLSI)已有相當的成果（附件一）。因此，我們希望能開發出適用的金屬閘極材料並獲得適合應用於n 型金屬閘極/ 高介電係數介電質金氧半電晶體場效上的有效功函數：4.2 eV 以及適合應用於p型金屬閘極/高介電係數介電質金氧半場效電晶體上的有效功函數：4.9eV~5.1 eV。由於計畫主持人-荊教授近幾年來與加拿大國家研究中心的S.P. McAlister 教授在奈米電子元件方面的研究合作已有相當的成果（已發表數十篇論文在國際知名期刊和會議，附件二），所以，在此研究計畫中，我們將繼續與加拿大國家研究中心合作。此外，我們也將與新加坡國立大學- 國家奈米元件實驗室（SNDL）合作。新加坡國立大學-國家奈米元件實驗室是目前在固態電子元件領域最傑出的學術研究單位之一（附件三），基於雙方友好的關係與之前合作的前例，相信會有很大的收穫與進展。最後，此計畫也將由國立交通大學張俊彥校長及電資學院吳重雨院長所共同協助指導與背書。
前瞻矽奈米元件變異性及傳輸特性綜合研究(I)
(2009)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載子傳輸特性，進行綜合研究。在工作項目一中，我們將分別對超薄基體(UTB)，多閘極(multi-gate)以及gate-all-around 奈米線金氧半場效電晶體，建立一套包含Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子效應的解析解模型，我們將研究這三種元件結構並搭配不同的通道材料，其對製程變異的敏感度。我們的元件模型也將有助於未來奈米級元件的設計。在工作項目二中，我們將廣泛地研究先進CMOS 場效電晶體的隨機不匹配特性(random mismatch)。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助於對奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在工作項目三中，我們將對奈米級應變矽元件的戴子傳輸特性進行研究。這項研究將有助於了解極微縮應變矽元件的戴子傳輸機制，也對未來提昇戴子遷移率的元件設計有所幫助。
高性能互補式金氧半影像感測器、矽視網膜及具學習能力之影像處理類神經網路晶片系統設計研究(I)
(2000)
吳重雨
;
CHUNG-YUWU
;
交通大學電子工程系

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