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A 918MHz Wide-Range CMOS Rectifier with Diode-Feeding and Switch-Capacitor-Based Load Modulation Technique
(2019-01-01)
Kuo, Chen-Yi
;
Lu, Chun-An
;
Liao, Yu-Te
;
交大名義發表
;
National Chiao Tung University
This paper presents a wide-input-range rectifier design with a diode-feeding (DF) architecture and load modulation. Dynamically-biased diodes are connected to the gates of the rectifying transistors to create bias voltage differences for PMOS and NMOS devices and the isolation of the reverse currents at different input power levels. Also, the switch-capacitor-based load modulation scheme is proposed to achieve optimal efficiency over wide-range load current deviations automatically. The proposed four-stage rectifier design was fabricated using 65nm CMOS technology and occupies a silicon area of 0.92 x 0.27mm(2). The measured sensitivity of the rectifier is -15dBm at 1M Omega load, and the peak power conversion efficiency is 28% at a load of 22k Omega With the load modulation scheme, the conversion efficiency is enhanced by >10% in a load current from 7 mu A to 35 mu A, when compared to a design without the load modulation scheme.
Differential Low Noise Amplifier for S-Band Phased-Array Radar in 0.18-mu m CMOS Technology
(2019-01-01)
Hsia, Tzu-Yu
;
Li, Xin-Yi
;
Yang, Liang-Yu Ou
;
Tsai, Zuo-Min
;
Chen, Shih-Yuan
An S-hand differential low noise amplifier (DLNA) is presented and implemented in TSMC 0.18-mu m CMOS process for use in the receiver of a phased-array radar. A special layout approach is used in the input matching circuit by integrating two individual inductors together to shrink the chip area while increasing the inductances. The 3-dB gain bandwidth of the two-stage DLNA ranges from 1.9 to 4 GHz (72.41%). The measured gain is about 18.5 dB with an average in-band noise figure of 5.77 dB. The chip area is 0.4672 mm(2).
A 94 GHz 10.8 mW Low-Noise Amplifier With Inductive Gain Boosting in 40 nm Digital CMOS Technology
(2019-01-01)
Yeh, Po-Chen
;
Kuo, Chien-Nan
;
交大名義發表
;
National Chiao Tung University
A W-band low-power, low-noise amplifier is designed and fabricated in 40 nm digital CMOS technology. The method of inductive gain boosting is utilized without extra power consumption. The circuit only consumes 10.8 mW dc power with a supply voltage of 1 V. The measured peak power gain achieves 14.5 dB at 93 GHz, while the minimum noise figure is 6.4 dB at 89 GHz. The circuit occupies a core area of only 0.07 mm(2).
Essential factors that affect bioelectricity generation byRhodopseudomonas palustrisstrainPS3in paddy soil microbial fuel cells
(1970-01-01)
Liu, Chia-Hung
;
Lee, Sook-Kuan
;
Ou, I-Che
;
Tsai, Kun-Ju
;
Lee, Yu
A plant-associated phototrophic bacterium,R. palustrisstrain PS3, was inoculated into a soil-based MFC to generate electricity. We evaluated the performance of this soil-based microbial fuel cell (MFC) and elucidated the essential factors that contributed to power generation. PS3 showed the potential to enhance power generation, especially when the apparatus was operated in a sealed chamber with illumination.We deduced that the improved power performance was due to the enhanced electron transport through the living electrode that was grown as a PS3 biofilm via photoheterotrophic metabolism. In addition, we suggested that the interplay between phototrophic fixation of ambient CO(2)and anaerobic oxidation of ferrous iron in soil was also involved in the increased power output. We implemented CMOS (complementary metal-oxide-semiconductor) technology with the soil-based MFC to harvest energy in a more efficient and stable manner. The above system is expected to provide a potentially low-cost and low-energy system with a high power conversion efficiency for practical applications in the future.
Wirelessly-Powered Printed Temperature Sensor with an Ultra-Low-Power and High-Sensitivity CMOS Readout IC
(2019-01-01)
Lu, Shao-Yung
;
Wu, I-Feng
;
Liao, Ying-Chih
;
Liao, Yu-Te
;
電機工程學系
This paper presents a wirelessly-powered high-sensitivity printed temperature sensor (TS). The proposed system consists of a -17dBm sensitivity RF-DC conversion circuit, a 2.2 mu W readout interface, and a printed NiO thermistor sensor. The 1 mm(2) printed NiO film has a good sensitivity index (B value) of 4000 K, but has high resistance (M Omega). The conventional readout system has difficulty detecting small resistance changes in the large thermal resistance range while only consuming a few microwatts, which is a need for enabling RF-power sensors remotely. A low-noise readout IC was designed to convert the resistance changes to digital codes. The proposed TS achieves a resolution of 0.04 degrees C/code in a temperature range of -20 degrees C to 90 degrees C, and measurement deviation within +/- 1.1%, while consuming only 2.2 nJ per conversion.
A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-finger nMOSFETs
(2018-01-01)
Guo, Jyh-Chyurn
;
Yeh, Kuo-Liang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.
A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS
(2019-01-01)
Sun, Wei-Che
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.
A W-Band 6.8 mW Low-Noise Amplifier in 90 nm CMOS Technology Using Noise Measure
(2019-01-01)
Yeh, Po-Chen
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A W-band low-noise amplifier consisting of seven common-source transistor stages is designed using noise measure as the figure of merit for circuit optimization. Fabricated in 90 nm CMOS technology, the die size is 0.38 mm(2), while the core active area only 0.1 mm(2). The circuit gives peak power gain of 21.5 dB at 90 GHz and noise figure of 8.3 dB, with dc power consumption of only 6.8 mW.
Signal Generation Techniques in CMOS for Millimeter-Wave and Terahertz Applications
(2019-01-01)
Hsieh, Cuei-Ling
;
Lin, Jung-Hsun
;
Yang, Chieh-Ying
;
Hsieh, Yi-Chun
;
Chen, Hong-Shen
This paper presents the design of three millimeter-wave and terahertz signal sources that demonstrates the feasibility of high performance signal source implemented in CMOS. A triple-push oscillator consisted of two antiparallel LC ring oscillators is presented with a low phase noise of -88 dBc/Hz at 1-MHz offset and a peak output power of -6 dBm at 210 GHz in a 90-nm CMOS process. An injection locked quadruple-push oscillator is then presented with a simulated output power of -16.3 dBm at 336 GHz and phase noise of -88 dBc/Hz at fundamental frequency in a 90-nm CMOS process. Lastly, a 330-GHz subharmonic injection locked frequency synthesizer is proposed. The core oscillator is based on the triple-push architecture. The frequency synthesizer achieves a simulated locking range of 5 GHz at 330 GHz with an output power of -8.6 dBm in a 40-nm CMOS process.
Ge FinFET CMOS Inverters With Improved Channel Surface Roughness by Using In-Situ ALD Digital O-3 Treatment
(2018-01-01)
Yeh, M. -S.
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Luo, G. -L.
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Hou, F. -J.
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Sung, P. -J.
;
Wang, C. -J.
Improved electrical characteristics of CMOS inverters composed of Ge n- and p-finFETs were demonstrated by utilizing newly introduced Ge surface treatments. In-situ digital O-3 treatment in ALD chamber was adopted on the surface of Ge fin sidewall in order to reduce the roughness and etching damages through the GeO desorption mechanism. The treatment effects were checked by AFM and C-V measurements. By combining this treatment with optimized microwave annealing, sub-threshold slope and the I-ON/I-OFF ratio were remarkably improved in both n-finFET and p-finFET, and Ge CMOS inverters with high voltage gain of 50.3 V/V at low V-D = 0.6 V was realized. Finally, simulations on an ideal Ge CMOS inverter were presented.

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