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Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
(2020-09-01)
Lin, Chih-Chih
;
Tai, Mao-Chou
;
Chang, Ting-Chang
;
Tsao, Yu-Ching
;
Wang, Yu-Xuan
In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.
Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs
(2020-01-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Chen, Chao-Hsuan
;
Sanyal, Indraneel
;
Tarng, Jenn-Hawn
A novel lattice matched double barrier Al0.72In0.16Ga0.12N/Al0.18In0.04Ga0.78N/GaN normally-off high electron mobility transistor (HEMT) is designed and simulated by solving a set of thermodynamic transport equations. Using the experimentally calibrated physical models with bearing mobility degradation by surface roughness in account, the recess gate and double barrier of the proposed device achieves a maximum drain current density (I-D,I-max) of 1149 mA/mm and a maximum transconductance (g(m,max)) of 358 mS/mm with a positive threshold voltage (Vth) of 0.2 V. The small polarization charge of first barrier is responsible for positive Vth. I-DS,I-max in the double barrier HEMT at high gate bias condition is due to injection of electrons from upper 2DEG which is almost impossible at lower gate voltage because of insufficient energy to cross the barrier. The injection of electrons is further supported by the second peak in the g(m) curve at low gate bias V-G = 1V. The outcome of this study suggests that the proposed device will be beneficial for high-frequency and high-power electronic applications.
Domain Adaptation With Foreground/Background Cues and Gated Discriminators
(2020-07-01)
Lin, Yong-Xiang
;
Tan, Daniel Stanley
;
Chen, Yung-Yao
;
Huang, Ching-Chun
;
Hua, Kai-Lung
Self-driving cars leverage on semantic segmentation to understand an urban scene. However, it is costly to collect segmentation labels, thus, synthetic datasets are used to train segmentation models. Unfortunately, the synthetic to real domain shift causes these models to perform poorly. Prior works use adversarial training to align features of both synthetic and real-world images. We observe that background objects tend to be similar across domains, while foreground objects tend to have more variations. Using this insight, we propose an adaptation method that uses foreground and background cues and adapt them separately. We also propose a mask-aware gated discriminator that learns soft masks from the input foreground and background masks instead of naively performing binary masking that immediately removes information outside of the predicted masks. We evaluate our method on two different datasets and show that our method outperforms several state-of-the-art baselines, which verifies the effectiveness of our approach.
Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors
(2020-08-01)
Huang, Shin-Ping
;
Chen, Hong-Chih
;
Chen, Po-Hsun
;
Zheng, Yu-Zhe
;
Chu, Ann-Kuo
The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.
Study of Charge Trapping Effects on AlGaN/GaN HEMTs Under UV Illumination With Pulsed I-V Measurement
(2020-06-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Chen, Bo-Yuan
;
Huang, Guo-Wei
;
Chuang, Chia-Wei
The charge trapping effects on AlGaN/GaN HEMTs under UV illumination are investigated using the pulsed current-voltage (I-V) measurement method. The test samples are unpassivated Schottky-gate HEMTs and metal-insulator-semiconductor HEMTs (MIS-HEMTs) with SiN gate dielectric. For HEMTs, the dominant charge trapping sources are the surface trap states, whereas, for MIS-HEMTs, they are trap states in the SiN gate dielectric and GaN buffer. When these devices are shined with the UV light, the drain current increases apparently in both samples owing to the generated photocurrent. By combining the UV illumination and pulsed I-V measurement, we find out the UV light has less effect on the surface charge trapping in the unpassivated HEMTs. Moreover, in MIS-HEMTs, we observe the charge trapping in the SiN gate dielectric becomes more serious under UV illumination, whereas the charge trapping in the GaN buffer is suppressed significantly. These findings are important for designing a GaN-based HEMT for photonic applications. In addition, the different responses of the surface-, buffer-, and gate-dielectric-related charge trapping to the UV light suggest that it would be easier to distinguish the trap types by introducing the UV illumination during the pulse measurement.
Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor
(2020-01-01)
Change, You-Tai
;
Tsai, Yueh-Lin
;
Peng, Kang-Ping
;
Su, Chun-Jung
;
Li, Pei-Wen
In this article, we investigate the four-level random telegraph noise (RTN) characteristics of a gate-all-around (GAA) nanowire (NW) transistor. The RTN-testing devices were fabricated with the sidewall spacer etching technique. The effective channel length and width are approximately 150 and 30 nm, respectively. By decoupling the four-level RTN, we are able to extract the time constants associated with the two traps. Circle-shaped approximations are used to mimic the triangular NW for evaluating the depths of the traps. The extracted depths of the two traps are very close to each other, which is consistent with the time-evolution measured results. We've also explored the probabilities of transitions between two specific current levels in the RTN characteristics, as well as the relative trapping/de-trapping frequencies.
Low-Frequency Noise Characterization of AlGaN & x002F;GaN HEMTs and MIS-HEMTs Under UV Illumination
(2020-01-01)
Nagarajan, Venkatesan
;
Chen, Kun-Ming
;
Lin, Hsin-Yi
;
Hu, Hsin-Hui
;
Huang, Guo-Wei
The low-frequency noise characteristics of AlGaN & x002F;GaN HEMTs and MIS-HEMTs are investigated in the dark condition and under UV illumination. The test devices with a 3-& x03BC;m-thick GaN buffer and a 25-nm-thick Al_0.22Ga_0.78N barrier layer were fabricated on the silicon wafer. For MIS-HEMTs, a 25-nm-thick SiN layer was deposited as a gate dielectric. The measured low-frequency noises show a 1 & x002F;f spectrum and can be described by the carrier number fluctuation model. Different noise responses to the UV light between HEMTs and MIS-HEMTs were observed. By comparing the noise data in dark and under UV illumination, the noise sources under the gate and in the ungated gate-drain access region have been identified. From these results, we can find a design guideline to improve the noise and reliability of GaN-based devices for optoelectronic applications.
Characteristics of Poly-Si Junctionless FinFETs With HfZrO Using Forming Gas Annealing
(2020-01-01)
Chung, Sheng-Ti
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
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電子物理學系
;
Department of Electrophysics
In this study, an effective method was proposed to enhance the current drivability of junctionless field-effect transistors (JL-FETs) by utilizing ferroelectric effects. The ferroelectric layers were deposited on JL-FinFETs. The poly-Si junctionless FinFETs (JL-FinFETs) with HfZrO were successfully fabricated and demonstrated. The subthreshold slope (S.S.) of JL-FinFETs with HfZrO was very sensitive to post-metal annealing (PMA) conditions and fin width. With PMA at 700 & x00B0;C, steeper S.S. and I_on& x002F;I_off> 10(7) could be obtained owing to the ferroelectric effect. JL-FinFETs with PMA at 700 & x00B0;C possessed lower I_off and offered the promise of higher integration flexibility for Si CMOS compatible process for future applications. Besides, the JL-FinFETs with forming gas annealing (FGA) had a small hysteresis and achieved the improved S.S.
Enhancement of Mechanical Bending Stress Endurance Using an Organic Trench Structure in Foldable Polycrystalline Silicon TFTs
(2020-05-01)
Zheng, Yu-Zhe
;
Huang, Shin-Ping
;
Chen, Po-Hsun
;
Chang, Ting-Chang
;
Tsai, Tsung-Ming
This letter proposes a new organic trench structure which can enhance the endurance of polycrystalline silicon thin film transistors (TFTs) under mechanical bending stress. It compares conventional structure TFTs to devices with an organic trench to examine reliability after undergoing 100,000 iterations of channel width-axis (100,000'WC) compression at R = 2mm. Due to the low Young's modulus of organic materials, stress while undergoing bending strain is desorbed to the buffer layer, which can lower the overall stress in TFTs. Furthermore, an optimal location and ideal length for such an organic trench is evaluated by mechanical bending simulation.
A Simple Control Strategy Extending Intrinsic Current Balancing Characteristics to Achieve a Full Operating Range for Interleaved Voltage-Doubler Boost DC-DC Converters
(2020-01-01)
Li, Chung-Yi
;
Chen, Tien-Hung
;
Chen, Hung-Chi
;
電機工程學系
;
電控工程研究所
The interleaved voltage-doubler boost converter strategy exhibits a very good performance, namely, in a low conduction loss, an acceptable switch stress, a fast transient response, and a very high power density. However, the bottleneck for application in the interleaved topology lies in the limit of operating duty ratio. In this article, an intrinsic current-balancing control method to achieve full operating range in duty ratio is proposed, and it can be easily implemented by including a voltage limiter to the conventional control configuration. With this novel design, both voltage-doubler and the current-balancing characteristics can be achieved within full range in duty cycle without any current sensor. The proposed method is implemented in a field programmable gate array chip. The provided simulations and experimental results validate the proposed method.

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