<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css"> Skip to main content

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作,涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 4 of 4
  • Item type:Item,
    Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
    (2017-06-01)
    Li, Zipeng
    ;
    Lai, Kelvin Yi-Tse
    ;
    Yu, Po-Hsien
    ;
    Chakrabarty, Krishnendu
    ;
    Ho, Tsung-Yi
    A digital microfluidic biochip (DMFB) is an attractive technology platform for automating laboratory procedures in biochemistry. In recent years, DMFBs based on a microelectrodedot- array (MEDA) architecture have been demonstrated. However, due to the inherent differences between today's DMFBs and MEDA, existing synthesis solutions for biochemistry mapping cannot be utilized for MEDA biochips. We present the first synthesis approach that can be used for MEDA biochips. We first present a general analytical model for droplet velocity and validate it experimentally using a fabricated MEDA biochip. We then present the proposed synthesis method targeting reservoir placement, operation scheduling, module placement, routing of droplets of various sizes, and diagonal movement of droplets in a two-dimensional array. Simulation results using benchmarks and experimental results using a fabricated MEDA biochip demonstrate the effectiveness of the proposed synthesis technique.
  • Item type:Item,
    Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip
    (2018-03-01)
    Li, Zipeng
    ;
    Lai, Kelvin Yi-Tse
    ;
    McCrone, John
    ;
    Yu, Po-Hsien
    ;
    Chakrabarty, Krishnendu
    A digital microfluidic biochip (DMFB) is an attractive technology platform for automating laboratory procedures in biochemistry. In recent years, DMFBs based on a microelectrode- dot-array (MEDA) architecture have been proposed. MEDA biochips can provide advantages of better capability of droplet manipulation and real-time sensing ability. However, errors are likely to occur due to defects, chip degradation, and the lack of precision inherent in biochemical experiments. Therefore, an efficient error-recovery strategy is essential to ensure the correctness of assays executed on MEDA biochips. By exploiting MEDA-specific advances in droplet sensing, we present a novel error-recovery technique to dynamically reconfigure the biochip using real-time data provided by on-chip sensors. Local recovery strategies based on probabilistic-timed-automata are presented for various types of errors. An online synthesis technique and a control flow are also proposed to connect local-recovery procedures with global error recovery for the complete bioassay. Moreover, an integer linear programming-based method is also proposed to select the optimal local-recovery time for each operation. Laboratory experiments using a fabricated MEDA chip are used to characterize the outcomes of key droplet operations. The PRISM model checker and three benchmarks are used for an extensive set of simulations. Our results highlight the effectiveness of the proposed error-recovery strategy.
  • Item type:Item,
    Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
    (2015-04-01)
    Yu, Shang-Tsung
    ;
    Yeh, Sheng-Han
    ;
    Ho, Tsung-Yi
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Electrowetting-on-dielectric (EWOD) chips have emerged as popular actuators for droplet-based digital microfluidic biochips. The chip-level design of EWOD chips allows for the integration electrode addressing and wire routing, thus helping cope with the increasing complexity of biochemical assays. Furthermore, high-frequency EWODs also facilitate finishing time-sensitive bioassays such as incubation and emerging flash chemistry in specific time periods. However, the reliability of the EWOD chip is reduced by the contact angle change reduction problem as a result of the repeated and frequent switching of electrodes. Thus, the chip-level design of EWOD chips should consider reliability, electrode addressing, and the wire routing problem. This paper presents a graph-based chip-level design algorithm. By setting the switching-time constraint, the number of switching times can be limited to minimize the impact of the contact angle change reductions problem. Also, a progressive addressing and routing approach is proposed to overcome the complex wire routing problem. Experimental results show the proposed algorithm effectively minimizes the impact of the contact angle change reduction problem, thus providing a reliable chip-level design with a feasible wire routing solution with the required number of pins.
  • Item type:Item,
    An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips
    (2015-04-01)
    Dinh, Trung Anh
    ;
    Yamashita, Shigeru
    ;
    Ho, Tsung-Yi
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Digital microfluidic biochips have become one of the most promising technologies for biomedical experiments. In modern microfluidic technology, reducing the number of independent control pins that reflects most of the fabrication cost, power consumption, and reliability of a microfluidic system, is a key challenge for every digital microfluidic biochip design. However, all the previous chip designs sacrifice the optimality of the problem, and only limited reduction on the number of control pins is observed. Moreover, most existing designs cannot satisfy high-throughput demand for bioassays, and thus inapplicable in practical contexts. In this paper, we propose the first optimal pin-count design scheme for digital microfluidic biochips. By integrating a very simple combinational logic circuit into the original chip, the proposed scheme can provide high-throughput for bioassays with an information-theoretic minimum number of control pins. Furthermore, to cope with the rapid growth of the chip\'s scale, we also propose a scalable and efficient heuristics to reduce the number of control pins. A logic optimization technique, which can be used to reduce the complexity of the integrated combinational logic circuit, is also presented in this paper. Experiments demonstrate that the proposed scheme can obtain much fewer number of control pins compared with the previous state-of-the-art works.