🏛️國立陽明交通大學機構典藏

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Reduction of Contact Resistivity by Nano-Textured Contact
(1970-01-01)
Tsui, Bing-Yue
;
Lee, Ya-Hsin
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The feasibility of reducing contact resistance by adding nano-textures on the contact surface is evaluated by three-dimensional simulation. Upward and downward pyramids and hemispheres are considered, and the effects of contact area and electric field are discussed. The downward nano-texture has a stronger electric field than the upward nano-texture; thus the increasing contact area will be more effectively used and lead to a greater improvement effect. On the other hand, the electric field of the hemisphere nano-texture is lower than that of the pyramid nano-texture. With proper design, the nano-textured contact can effectively reduce contact resistance up to 30-50%. Therefore, the proposed nano-textured contact is a promising approach with contact resistivity approaching physical limits.
Ultralow Schottky Barriers in Hexagonal Boron Nitride-Encapsulated Monolayer WSe2 Tunnel Field-Effect Transistors
(2020-04-22)
Pande, Gaurav
;
Siao, Jyun-Yan
;
Chen, Wei-Liang
;
Lee, Chien-Ju
;
Sankar, Raman
To explore the potential of field-effect transistors (FETs) based on monolayers (MLs) of the two-dimensional semiconducting channel (SC) for spintronics, the two most important issues are to ensure the formation of variable low-resistive tunnel ferromagnetic contacts (FCs) and to preserve intrinsic properties of the SC during fabrication. Large Schottky barriers lead to the formation of high resistive contacts, and methods adopted to control the barriers often alter the intrinsic properties of the SC. This work aims at addressing both issues in fully encapsulated ML WSe2 FETs using bilayer hexagonal boron nitride (h-BN) as a tunnel barrier at the FC/SC interface. We investigate the electrical transport in ML WSe2 FETs with the current-in-plane geometry that yields hole mobilities of similar to 38.3 cm(2) V-1 s(-1) at 240 K and on/off ratios of the order of 10(7), limited by the contact regions. We have achieved an ultralow effective Schottky barrier (similar to 5.34 meV) with an encapsulated tunneling device as opposed to a nonencapsulated device in which the barrier heights are considerably higher. These observations provide an insight into the electrical behavior of the FC/h-BN/SC/h-BN heterostructures, and such control over the barrier heights opens up the possibilities for WSe2-based spintronic devices.
Graphene-Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits
(2020-01-01)
Yeh, Chao-Hui
;
Liang, Zheng-Yong
;
Lin, Yung-Chang
;
Chen, Hsiang-Chieh
;
Fan, Ta
The most pressing barrier for the development of advanced electronics based on two-dimensional (2D) layered semiconductors stems from the lack of site-selective synthesis of complementary n- and p-channels with low contact resistance. Here, we report an in-plane epitaxial route for the growth of interlaced 2D semiconductor monolayers using chemical vapor deposition with a gas-confined scheme, in which patterned graphene (Gr) serves as a guiding template for site-selective growth of Gr-WS2-Gr and Gr-WSe2-Gr heterostructures. The Gr/2D semiconductor interface exhibits a transparent contact with a nearly ideal pinning factor of 0.95 for the n-channel WS2 and 0.92 for the p-channel WSe2. The effective depinning of the Fermi level gives an ultralow contact resistance of 0.75 and 1.20 k Omega.mu m for WS2 and WSe2, respectively. Integrated logic circuits including inverter, NAND gate, static random access memory, and five-stage ring oscillator are constructed using the complementary Gr-WS2-Gr-WSe2-Gr heterojunctions as a fundamental building block, featuring the prominent performance metrics of high operation frequency (>0.2 GHz), low-power consumption, large noise margins, and high operational stability. The technology presented here provides a speculative look at the electronic circuitry built on atomic-scale semiconductors in the near future.
A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications
(1970-01-01)
Lin, Che-Yi
;
Chen, Chao-Fu
;
Chang, Yuan-Ming
;
Yang, Shih-Hsien
;
Lee, Ko-Chun
Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3Ge/Ge/Cu3Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 10(5) and 10(3) for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.
稀磁性半導體薄膜光學特性之研究與半導體微結構之理論探討(II)
(1996)
褚德三
;
CHUU DER SAN
;
國立交通大學電子物理學系

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