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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
    (2010-11-01)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology
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    A systematic optimized comparison algorithm for LDPC decoder
    (2008)
    Hung, Jui-Hui
    ;
    Hung, Jui-Hung
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper proposes a novel systematic optimized comparison algorithm for LDPC codes with arbitrary code lengths. Based on the presented algorithm, we also design a corresponding decoder architecture which has a short comparison delay time of [log(2)(n-1)] and a very low comparator complexity of n x [log(2) (n - 1)], where n is the input number to CNU. Besides, the proposed design is general, systematic and flexible, which can be applied to arbitrary input number of a CNU. The designed CNU is favorable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
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    A systematic optimized comparison algorithm for fast LDPC decoding
    (2007)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper proposes a novel systematic optimization algorithm for comparison operations required by a check node unit (CNU) in LDPC decoding, given any input number N-in. The algorithm can automatically synthesize an optimized fast comparison operations that guarantees a shortest comparison delay time of [log(2) (N-in - 1)] T-cmp and a minimized total number of two-input comparators, where T-cmp is the delay time of a comparator. High speed is achieved by adopting parallel divide-and-conquer comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that maximizes shareable comparison operations. The designed CNU is favourable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
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    A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard
    (2007)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.