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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-mu m 60-V/5-V BCD Technology
    (2017-08-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.
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    Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
    (2018-02-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The modified silicon-controlled rectifier (SCR) fabricated in a 0.25-mu m high-voltage (HV) bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective electrostatic discharge (ESD) protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high holding voltage of up to similar to 30 V in the 100-ns transmission line pulsing measurement results. However, through the experimental verification by using the transient latchup test, the holding voltage of such proposed device decreases to similar to 20 V. It is due to the increased bipolar junction transistor current gains of the SCR path induced by the Joule-heating effect in the long-term measurement. For 20-V circuit applications, the ESD robustness of the proposed SCR with a holding voltage of similar to 20 V is lower than that of stacked low-voltage p-type MOS in the previous studies. Developing special modification of such HV devices is inefficient to achieve both effective ESD protection and latchup-free design in this 0.25-mu m HV BCD technology.
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    ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
    (2017-02)
    Ker, Ming-Dou
    ;
    Chiu, Po-Yen
    ;
    Shieh, Wuu-Trong
    ;
    Wang, Chun-Chi
    ;
    電子工程學系及電子研究所
    Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of +/- 15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.
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    Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process
    (2016-06)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The optimization of guard ring structures to improve latchup immunity in an 18 V double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has together been investigated in a silicon test chip. The layout parameters including the anode-to-cathode spacing and the guard ring width are also studied to seek their impacts on latchup immunity. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity. The suggested guard ring structures can be applied to the high-voltage circuits in this 18 V DDDMOS process to meet the new Joint Electron Device Engineering Council standard (JESD78D) with the trigger current of over +/- 200 mA.