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    A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
    (2019-08-01)
    Lee, Yuan-Sheng
    ;
    Ho, Wei-Hsiang
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2(31)-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm(2). The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
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    A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
    (2019-08-01)
    Lee, Yuan-Sheng
    ;
    Ho, Wei-Hsiang
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2x oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 231-1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about -13.8 and -8.7 dBm respectively, for a bit error rate (BER) of less than 10(-12). The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm2. The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.
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    A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery
    (2018-01-01)
    Lee, Yuan-Sheng
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A single chip optical receiver comprising of a font-end amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 2(31)-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10(-12) (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm(2). It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.
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    A 25 Gb/s 1.13 pJ/b-10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS
    (2017-03-01)
    Huang, Shih-Hao
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper describes the design of a 25 Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current-boosting preamplifier with a dual-path time-interleaved integrating-type optical receiver, it provides 1:2 demultiplexing operation with a tolerance to lower bandwidth photodiodes. The bandwidth of current amplifier is chosen as 0.35x operating data rate for maximizing the receiver signal-to-noise ratio. Experimental results show that the receiver can achieve 25 Gb/s operation when integrated with a 9 or 17 GHz GaAs photodiode. Input sensitivities in the two cases are -7.2 dBm (w/i a 9 GHz photodiode) and -10.8 dBm (w/i a 17 GHz photodiode), respectively, for a bit error rate of less than 10(-12). In addition, a single-tap decision-feedback equalizer (DFE) is embedded to compensate photodiode bandwidth and improve input sensitivity. Integrated with a low-cost 9 GHz photodiode, the input sensitivity and timing margin of the receiver are improved by 2 dB and 0.25 UI, respectively, after DFE compensation. By utilizing a current integrator and time-interleaved comparators, its energy efficiency is 1.13 pJ/b at 25 Gb/s under a 1.2 V power supply. Fabricated in a 40 nm bulk-CMOS technology, the core circuit occupies a chip area of 0.007 mm(2) only.
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    Multichannel Receiver and AGC for Optical Links
    (2016)
    Huang, Shi-Hao
    ;
    Lai, Shen-Hua
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Multi-channel, fully integrated CMOS optical receivers combining with spatially modulated photo detector (SMPD) array, transimpedance amplifiers, and limiting amplifiers are presented. It demonstrates scalable channel numbers with minimum area overhead and low cross talk of less than 0.1 dB. The receiver array is implemented in 0.18 mu m CMOS and provides 20 Gbps throughput (5Gbps x 4). The conversion gain of each channel is 116 dB Omega, and the input sensitivity is about -11dBm for BER of less than 10(-12). Besides, a 10 Gbps receiver with automatic gain control (AGC) for TIA is proposed. It tolerates 15 dB dynamic range, and the gain peaking can be improved by more than 3dB.
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    A 25-Gb/s,-10.8-dBm Input Sensitivity, PD-Bandwidth Tolerant CMOS Optical Receiver
    (2015)
    Huang, Shih-Hao
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities in the two cases are -7.2 dBm (w/i 9-GHz PD) and -10.8 dBm (w/i 17-GHz PD) respectively for BER of less than 10(-12). The energy efficiency is 1.13 pJ/bit. Fabricated in TSMC 40-nm CMOS technology, the core circuit occupies a chip area of 0.007 mm(2) only.
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    光通訊類比前端積體電路設計
    (2008)
    蔡嘉明
    ;
    Tsai Chia-Ming
    ;
    國立交通大學電子工程學系及電子研究所
    本計畫將針對850nm 高速乙太網路光通訊系統應用，以標準CMOS 製程技術 開發其接收端與發射端最關鍵的類比前端積體電路，其接收端包含檢光二極體、轉 阻放大器、限幅放大器、以及可提供補償功能的等化器等，其發射端則主要為一雷 射驅動器，此類比前端積體電路之性能乃是整個光纖網路系統性能的重要瓶頸。在 各種放大器之設計上本計畫將運用負阻抗補償技術以求同時改善增益與頻寬兩者 之性能；此外，為補償CMOS 檢光二極體之非理想頻率響應特性，本計畫將結合適 應性等化器之設計架構，以實現自動最佳化補償之功能，並可藉此降低因製程、電 壓、或是溫度變化所造成之性能劣化。關於雷射驅動器部分，其主要研究工作則著 重於自動功率控制功能之數位化設計、以及適用於低電壓CMOS 製程之主動式阻抗 匹配技術之開發。本計畫之最終目的為開發出可適用於continuous-mode 與 burst-mode 系統之整合型光接收器與高整合度之雷射驅動器。
  • Thumbnail Image
    Item type:Item,
    光通訊類比前端積體電路設計
    (2007)
    蔡嘉明
    ;
    Tsai Chia-Ming
    ;
    國立交通大學電子工程學系及電子研究所
    本計畫將針對850nm 高速乙太網路光通訊系統應用，以標準CMOS 製程技術 開發其接收端與發射端最關鍵的類比前端積體電路，其接收端包含檢光二極體、轉 阻放大器、限幅放大器、以及可提供補償功能的等化器等，其發射端則主要為一雷 射驅動器，此類比前端積體電路之性能乃是整個光纖網路系統性能的重要瓶頸。在 各種放大器之設計上本計畫將運用負阻抗補償技術以求同時改善增益與頻寬兩者 之性能；此外，為補償CMOS 檢光二極體之非理想頻率響應特性，本計畫將結合適 應性等化器之設計架構，以實現自動最佳化補償之功能，並可藉此降低因製程、電 壓、或是溫度變化所造成之性能劣化。關於雷射驅動器部分，其主要研究工作則著 重於自動功率控制功能之數位化設計、以及適用於低電壓CMOS 製程之主動式阻抗 匹配技術之開發。本計畫之最終目的為開發出可適用於continuous-mode 與 burst-mode 系統之整合型光接收器與高整合度之雷射驅動器。