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    Power Analysis and Sample Size Planning in ANCOVA Designs
    (2020-03-01)
    Shieh, Gwowen
    ;
    交大名義發表
    ;
    管理科學系
    ;
    National Chiao Tung University
    ;
    Department of Management Science
    The analysis of covariance (ANCOVA) has notably proven to be an effective tool in a broad range of scientific applications. Despite the well-documented literature about its principal uses and statistical properties, the corresponding power analysis for the general linear hypothesis tests of treatment differences remains a less discussed issue. The frequently recommended procedure is a direct application of the ANOVA formula in combination with a reduced degrees of freedom and a correlation-adjusted variance. This article aims to explicate the conceptual problems and practical limitations of the common method. An exact approach is proposed for power and sample size calculations in ANCOVA with random assignment and multinormal covariates. Both theoretical examination and numerical simulation are presented to justify the advantages of the suggested technique over the current formula. The improved solution is illustrated with an example regarding the comparative effectiveness of interventions. In order to facilitate the application of the described power and sample size calculations, accompanying computer programs are also presented.
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    Power analysis for group supplier selection with multiple production lines
    (2018-12-01)
    Pearn, W. L.
    ;
    Tai, Y. T.
    ;
    Wu, Yu-Wen
    ;
    Wang, Yuan-An
    ;
    工業工程與管理學系
    Group supplier selection problem is a critical problem because outsourcing is an important issue for supply chain management. For the advanced production processes with extremely low fraction of defectives, typical supplier selection methods no longer work because any sample of reasonable size probably contains no defective items. Thus, process capability indices have been extensively used for advanced production processes to evaluate and measure whether the process meets the specifications and they also provide quality assurance. In the globally competitive production environment, processes involving multiple production lines are quite common due to economies of scale considerations. In this paper, we consider a group supplier selection problem for multi-supplier and multi-line, in which a supplier group containing the best suppliers is selected based on a multi-line yield index CpkM. To avoid the inflation of multiple comparisons, we apply the Bonferroni method and subtraction test statistic to tackle the group supplier selection problem. Critical values for testing procedure and required sample sizes for designated selection powers are obtained and tabulated. In addition, we apply multiple comparisons with the best method and compare the selection powers with the Bonferroni method for various power settings to provide more accurate group supplier decisions for real-world applications.
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    Determining Sample Size With a Given Range of Mean Effects in One-Way Heteroscedastic Analysis of Variance
    (2013-07-03)
    Shieh, Gwowen
    ;
    Jan, Show-Li
    ;
    交大名義發表
    ;
    管理科學系
    ;
    National Chiao Tung University
    The authors examined 2 approaches for determining the required sample size of Welch's test for detecting equality of means when the greatest difference between any 2 group means is given. It is shown that the actual power obtained with the sample size of the suggested approach is consistently at least as great as the nominal power. However, the sample size given by the method of Guo and Luh (2008) does not always guarantee the minimum power performance. Furthermore, the computed sample size and associated power of their formula tend to be larger than those provided with the proposed procedure. A supplementary computer program is provided to aid the implementation of the proposed technique in planning analysis of variance designs.
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    Optimal Sample Size Determinations for the Heteroscedastic Two One-Sided Tests of Mean Equivalence: Design Schemes and Software Implementations
    (2017-04-01)
    Jan, Show-Li
    ;
    Shieh, Gwowen
    ;
    管理科學系
    ;
    Department of Management Science
    Equivalence assessment is becoming an increasingly important topic in many application areas including behavioral and social sciences research. Although there exist more powerful tests, the two one-sided tests (TOST) procedure is a technically transparent and widely accepted method for establishing statistical equivalence. Alternatively, a direct extension of Welch's solution for the Behrens-Fisher problem is preferred in equivalence testing of means when the homogeneity of variance assumption is violated. For advance planning of equivalence studies, this article describes both exact and nearly exact power functions of the heteroscedastic TOST procedure and develops useful approaches to optimal sample size determinations under various allocation and cost considerations. Detailed numerical illustrations and simulation studies are presented to demonstrate the distinct features of the suggested techniques and the potential deficiency of existing method. Moreover, computer programs are provided to facilitate the implementation of the described sample size procedures. The proposed formulas and algorithms are recommended over the current results for their technical transparency, overall performance, and diverse utility.
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    Sample Size Determination for Examining Interaction Effects in Factorial Designs Under Variance Heterogeneity
    (2018-03-01)
    Shieh, Gwowen
    ;
    交大名義發表
    ;
    管理科學系
    ;
    National Chiao Tung University
    ;
    Department of Management Science
    Moderation analysis is a vital aspect of research in education, management, psychology, and related disciplines. Although several methodological artifacts have been identified and examined, heterogeneity of variance remains one of the unique and problematic factors known as detrimental to statistical power in the detection of moderating effects. To alleviate the difficulty in assessing moderation because of low statistical power, this article describes feasible solutions to sample size calculations for tests of hypothesized interactions between categorical variables under variance heterogeneity. Detailed numerical illustrations and simulation studies are presented to demonstrate the feature and usefulness of the suggested technique for 2- and 3-way factorial designs. Moreover, SAS and R programs are provided to facilitate the implementation of the proposed sample size procedure.
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    Power and Sample Size Calculations for Contrast Analysis in ANCOVA
    (2017)
    Shieh, Gwowen
    ;
    管理科學系
    ;
    Department of Management Science
    Analysis of covariance (ANCOVA) is commonly used in behavioral and educational research to reduce the error variance and improve the power of analysis of variance by adjusting the covariate effects. For planning and evaluating randomized ANCOVA designs, a simple sample-size formula has been proposed to account for the variance deflation factor in the comparison of two treatment groups. The objective of this article is to highlight an overlooked and potential problem of the exiting approximation and to provide an alternative and exact solution of power and sample size assessments for testing treatment contrasts. Numerical investigations are conducted to reveal the relative performance of the two procedures as a reliable technique to accommodate the covariate features that make ANCOVA design particularly distinctive. The described approach has important advantages over the current method in general applicability, methodological justification, and overall accuracy. To enhance the practical usefulness, computer algorithms are presented to implement the recommended power calculations and sample-size determinations.
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    A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry
    (2016-10)
    Chiang, Chien-Hsueh
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    Li, Yiming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    In this study, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display. The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a five-mask amorphous silicon process for thin-film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving method. Moreover, the minimum operation high voltage keeps the same level of the ASG circuit with the new clock driving. Notably, the proposed driving method causes merely 5.5% increment of the power consumption, compared with the conventional one.
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    Design Optimization of 16-nm Bulk FinFET Technology via Geometric Programming
    (2014-01-01)
    Su, Ping-Hsun
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    Li, Yiming
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.
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    奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫一：奈米CMOS射頻與混合訊號模型研發應用於超低功耗與低雜訊設計
    (2008)
    郭治群
    ;
    Guo Jyh-Chyurn
    ;
    國立交通大學電子工程學系及電子研究所
    奈米 CMOS 技術之精進已面臨諸多極限問題，如元件線寬之持續微縮，操作電壓 之降低，動態範圍，雜訊與功耗等。其中低功耗與低雜訊，乃是元件模型與電路設計 領域中最具挑戰性的兩個課題。本計劃擬提出創新的元件與電路操作方法，利用異於 傳統之偏壓結構，以解決CMOS 元件臨界電壓與操作電壓之極限問題，並實現低功耗 與低雜訊之設計。目標為微瓦級之超低功耗，以應用於無線可穿戴式之生醫檢測系統。 此創新之偏壓架構乃以四端元件配合四埠測試結構為基礎，並提出｢動態基極偏壓｣方 法為一最佳方案，以兼顧操作功耗與靜止功耗，並有效應用於奈米CMOS 元件與電路 設計。再者，四端元件可提供較大之操作自由度，例如可同時施加直流與射頻訊號於 各個獨立端點。基於此新穎特性，應用於射頻與混合訊號技術平台，可創造出新的電 路架構，以達超低功耗與低雜訊之目標。 奈米CMOS 技術應用於射頻與混合訊號電路，雜訊乃是另一重要課題，需考量極 低頻至極高頻之特性。極小元件之雜訊量測，乃是高難度的工作，因其雜訊往往夾雜 來自矽基板、探針墊、與傳輸線之耦合效應。因此，如何有效且準確萃取元件之本質 雜訊乃是最基本之核心技術。本實驗室於上一期三年計畫已完成一套創新的｢lossy substrate model｣，可準確萃取奈米元件之本質雜訊。本計劃以此為基礎，將進一步研 究雜訊阻隔法，利用奈米射頻CMOS 技術與先進後段製程研製各種結構，測試其雜訊 阻隔能力與效果，並以驗證過之lossy substrate model 為基礎，開發一可模擬雜訊阻隔 效應之等效電路模型，以正確預測各種奈米元件搭配不同雜訊阻隔結構之效果，同時 可模擬四端元件中動態基極偏壓對於雜訊之影響。 前述研究主題隨之產生新的挑戰與研究子題，如量測、去寄生效應、參數萃取、 與模型開發等。傳統標準之射頻CMOS 模型僅限於三端元件模擬，不適用於四端元件 加上動態基極偏壓。針對射頻與混合訊號電路設計所需模型，其新的研究課題可歸納 為 (1) 次截止區之I-V 模型 : 動態基極偏壓對VT、swing、IOFF 之效應。 (2) 線性與飽和區之I-V 模型 : 動態基極偏壓對於mobility、body charge factor、short channel effects、body RC network 與 self-heating effect 之影響。 (3) 四端元件之C-V 模型 : 動態基極偏壓對於gate capacitance、junction capacitance 與 drain-to-source coupling capacitance 之效應。 (4) 四端元件之雜訊模型 : channel 與gate 電流之熱雜訊於寬頻區間且動態基極偏壓 操作下之特性。Flicker 雜訊於截止區加上動態基極偏壓操作之效應。 本三年計劃擬實現之成果為 (1) 第一年(2008~2009) (a) 建立一完整的四端元件與四埠測試結構與分析方法，研究動態基極偏壓之效應 與最佳化設計。 (b) 建立雜訊阻隔結構與低雜訊量測系統、方法，可適用於極寬頻與不同操作電壓 之量測分析。 (2) 第二年(2009~2010) (a) 開發一套射頻CMOS 元件模型，可準確模擬四端元件於動態基極偏壓下之特 性。此模型可適用於標準電路模擬軟體，以輔助超低功耗之射頻電路設計。 (b) 完成一套寬頻且可微縮之lossy substrate model，以正確模擬奈米元件雜訊特性 與雜訊阻隔效應。此模型可適用於射頻電路模擬軟體，輔助低雜訊電路設計。 (3) 第三年(2010~2011) (a) 設計完成超低功耗射頻電路，包括LNA，mixer 與VCO，應用驗證之動態基極 偏壓法。其低功耗規格為LNA+mixer < 0.5mW 以應用於無線近身網路(wireless body area network)。 (b) 設計完成低雜訊射頻電路，包括LNA，mixer 與VCO，應用雜訊阻隔法與動態 基極偏壓。其低雜訊規格為LNA≤ 2dB，mixer ≤ 8dB。至於VCO，其相位雜訊 規格為−110 dBc / Hz於1MHz offset 操作下。
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    Impact of hot carrier stress on RF power characteristics of MOSFETs
    (2005)
    Huang, SY
    ;
    Chen, KM
    ;
    Huang, GW
    ;
    Yang, DY
    ;
    Chang, CY
    This paper investigates hot-carrier (HQ effects on the RF power and linearity characteristics of MOS transistors using load-pull measurement. We found that the RF power characteristics are affected by the HC stress, and the linearity of MOS transistors is clearly degraded after HC stress at constant gate voltage measurement. However, at high gate voltage bias, the HC-induced power degradation is much reduced compared with that under low gate voltage regimes. In addition, HC effects on linearity can be softened by biasing the transistor at constant drain currents. These experimental observations can be explained by the change of threshold voltage, transconductance, subthreshold swing, and mobility degradation coefficient under HC stress.