<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Filters

2003 - 200932010 - 20133

Settings

🏛️國立陽明交通大學機構典藏

Has files: YesSubject: search.filters.subject.Ge

Search Results

Now showing 1 - 6 of 6
  • Thumbnail Image
    Item type:Item,
    Growth of high-quality Ge epitaxial layers on Si(100)
    (2003-05-15)
    Luo, GL
    ;
    Yang, TH
    ;
    Chang, EY
    ;
    Chang, CY
    ;
    Chao, KA
    A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum.
  • Thumbnail Image
    Item type:Item,
    Controlled placement of self-organized Ge dots on patterned Si (001) surfaces
    (2004-02-15)
    Lee, HM
    ;
    Yang, TH
    ;
    Luo, GL
    ;
    Chang, EY
    ;
    材料科學與工程學系
    The positioning and ordering of the self-organized Ge dots were controlled using the ultra high-vacuum chemical molecular epitaxial growth of Ge on electron beam lithographically patterned Si (001) substrates. The experimental results indicate that the edge smoothness of the etched Si holes affects the distribution and long-range ordering of the Ge dots formed. With optimized etching conditions, the Ge dots can be grown uniformly on the edges of the holes etched on the patterned Si substrates. The sizes of the Ge dots are approximately 10 nm. The proposed, technique can be applied to the fabrication of regimented arrays in signal processing applications.
  • Thumbnail Image
    Item type:Item,
    Al2O3-Ge-On-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates
    (2004-03-01)
    Yu, DS
    ;
    Huang, CH
    ;
    Chin, A
    ;
    Zhu, CX
    ;
    Li, MF
    High-kappa, A1(2)O(3)/Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the A1(2)O(3)-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with A1(2)O(3)-Si MOSFETs. Additionally, A1(2) O-3-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than A1(2)O(3)-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500 degreesC rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-kappa to minimize interfacial reactions and crystallization of the high-kappa material, and oxygen penetration in high-kappa MOSFETs.
  • Thumbnail Image
    Item type:Item,
    High-field mobility metal-gate/high-kappa Ge n-MOSFETs with small equivalent-oxide-thickness
    (2011-01-01)
    Chen, W. B.
    ;
    Cheng, C. H.
    ;
    Lin, C. W.
    ;
    Chen, P. C.
    ;
    Chin, Albert
    We fabricated high performance gate-last TaN/La(2)O(3)/SiO(2) on Ge n-MOSFET. Small equivalent-oxide-thickness (EOT) of 1.9-nm and high-field mobility of 258 cm(2)/V s at 0.75 MV/cm were obtained, which were attributed to the thin SiO(2)-like barrier layer and low process temperature to prevent interfacial reaction during post-deposition annealing (PDA). (C) 2010 Elsevier Ltd. All rights reserved.
  • Thumbnail Image
    Item type:Item,
    Metal-Gate/High-kappa/Ge nMOS at Small CET With Higher Mobility Than SiO2/Si at Wide Range Carrier Densities
    (2013-02-01)
    Liao, C. C.
    ;
    Ku, T. C.
    ;
    Lin, M. H.
    ;
    Zeng, Lang
    ;
    Kang, Jinfeng
    High-performance TaN/TiLaO/La2O3/SiO2/(111)-Ge nMOSFETs show high mobility of 432 cm(2)/V . s at 10(13) cm(-2) carrier density (N-s), good 1.05 junction ideality factor, and small subthreshold swing of 101 mV/dec, at a small 1.1-nm capacitance-equivalent thickness (CET). This is the first report of higher mobility in the Ge nMOSFET than SiO2/Si universal mobility at wide medium-high N-s range and small CET of 1.1 nm, which is attributed to using the (111)-Ge substrate, 30-ns laser annealing, SiO2 interfacial layer, and YbGex/n-Ge contact.
  • Thumbnail Image
    Item type:Item,
    Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing
    (2011-04-01)
    Chen, W. B.
    ;
    Shie, B. S.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO(2)/La(2)O(3)/SiO(2) on Ge n-MOSFETs shows a high gate capacitance density, a small n(+)/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm(2)/V . s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO(2)/Si universal mobility.