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極低蕭基位障與接觸電阻技術之研究(I)
(2010)
崔秉鉞
;
Tsui Bing-Yue
;
國立交通大學電子工程學系及電子研究所
隨金氧半場效電晶體的尺寸不斷微縮，金屬與源極/汲極的接觸面積也持續縮小，接觸電阻在整體電晶體的寄生電阻中所佔的比例將會持續上升。欲降低接觸電阻係數，必須提高接面載子濃度以及降低蕭基位障接面高度。然載子濃度受限於製程溫度及元素在基板中的固態溶解度，除非更換基板材料，不容易再提高，降低蕭基位障高度便成為當務之急。本三年期計畫包含四個部分：極低蕭基位障高度的參數擷取與製程技術、極低接觸電阻係數的參數擷取與製程技術、三維物性/化性/模擬分析技術、低寄生電阻奈米電晶體整合技術。第一年度以建立極低蕭基位障高度以及極低接觸電阻係數的參數擷取技術為主，以便驗證後續製程技術開發的成效。本年度並將完成蕭基位障元件製作以及接觸電阻係數的測試結構的設計，並嘗試幾種降低蕭基位障高度的技術。第二年度將延續第一年的進度，尋求將蕭基位障高度降低到0.4eV 以下，接觸電阻係數3 Ω-μm2 以下的材料與製程技術，並對各種製程的調變機制進行深入的理論分析。第三年度將整合前兩年度所發展的低蕭基位障高度以及低接觸電阻技術於奈米尺度電子元件之製作，以驗證降低接觸電阻對於提升元件性能的作用。本計畫可以產出蕭基位障高度低於0.4eV、接觸電阻係數低於3 Ω-μm2 的材料與製程技術，並在30nm 以下的電晶體驗證。此計畫規格符合2007 年ITRS 預估的2016 年需求，極具學術與產業應用價值。
肖基障金氧半場效体之數值模擬
(2001)
郭雙發
;
國立交通大學電子工程學系
The effects of growth temperature on the microstructure and electrical barrier height in PtSi/p-Si(100) Schottky barrier detector
(2000-10-03)
Horng, GJ
;
Chang, CY
;
Ho, C
;
Lee, CY
;
Huang, TY
The effects of growth temperature on the microstructure and electrical barrier height of the PtSi Schottky barrier detector (SBD) have been investigated. PtSi films, 4 nm in thickness were deposited at various temperatures ranging from 350 to 550 degreesC. The electron diffraction patterns showed that PtSi film formed at 350 degreesC depicts an intermingling of both (1 (1) over bar1) and (1 (2) over bar1) orientations. However, only (1 (2) over bar1) orientation was shown when the PtSi films were formed above 450 degreesC. Moreover, SBD formed at 350 degreesC was found to depict an electrical barrier that is approximately 0.02 eV higher than those formed above 450 degreesC. Although the microstructure and the electrical barrier height of the PtSi film do not change when the formation temperature was further increased from 450 to 550 degreesC. Nevertheless, the higher formation temperature resulted in a larger grain size, indicating that grain size alone does not affect the barrier height of the resultant SBD. (C) 2000 Elsevier Science S.A. All rights reserved.
Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension
(2001-04-01)
Lin, HC
;
Yeh, KL
;
Huang, RG
;
Lin, CY
;
Huang, TY
A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on-off current ratio, the new device exhibits high on/off current ratio up to 10(6) for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
Ambipolar Schottky-barrier TFTs
(2002-02-01)
Lin, HC
;
Yeh, KL
;
Huang, TY
;
Huang, RG
;
Sze, SM
A novel Schottky-barrier metal-oxide-semiconductor thin-film transistor (SBTFT) was successfully demonstrated and characterized. The new SBTFT device features a fleld-induced-drain (FID) region, which is controlled by a metal field-plate lying on top of the passivation oxide. The FED region is sandwiched between the silicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. The device is thus capable of ambipolar operation. Excellent ambipolar performance with on/off current ratios over 10(6) for both p- and n-channel operations was realized simultaneously on the same device fabricated with polysilicon active layer. Moreover, the off-state leakage current shows very weak dependence on the gate-to-drain voltage difference with the FID structure. Finally, the effects of FED length are explored.
Reduction of off-state leakage current in Schottky barrier thin-film transistors (SBTFT) by a field-induced drain
(2002-04-01)
Yeh, KL
;
Lin, HC
;
Huang, RG
;
Tsai, RW
;
Huang, TY
Detailed conduction mechanisms in a conventional Schottky barrier thin-film transistor (SBTFT) and a recently proposed novel SBTFT with field-induced drain (FID) extension have been studied. The new SBTFT device with FID extension shows excellent ambipolar performance with effective suppression of gate-induced drain leakage (GIDL)-like off-state leakage that plagues conventional SBTFT devices. By characterizing the activation energy of the conduction process in the off-state for conventional SBTFT devices, it is suggested that field emission of carriers from the drain junction is the major conduction mechanism. While for the FID SBTFT devices, owing to the effect of Fermi level pinning in the FID region, thermionic emission rather than field emission becomes the dominant conduction mechanism, resulting in the effective suppression of the undesirable GIDL-like leakage current.
Application of field-induced source/drain Schottky metal-oxide-semiconductor to fin-like body field-effect transistor
(2002-06-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Liu, JT
;
Huang, TY
A novel Schottky barrier silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) device was proposed and demonstrated, The new device features a silicide source/drain and field-induced source/drain (S/D) extensions. Excellent ambipolar performance with a near-ideal sub-threshold slope (similar to 60 mV/decade) and high on-/off-state current ratio (comparable to or higher than 10(9)) is realized, for the first time, on a single device. These encouraging results suggest that the new device may be suitable for some niche applications requiring simple and low-temperature processing of complementary metal-oxide-semiconductor(CMOS)-like devices.
Ambipolar Schottky barrier silicon-on-insulator metal-oxide-semiconductor transistors
(2003-02-01)
Lin, HC
;
Wang, MF
;
Lu, CY
;
Huang, TY
;
電子工程學系及電子研究所
A novel Schottky barrier silicon-on-insulator metal-oxide-semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10(8) and 10(7) are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. (C) 2002 Elsevier Science Ltd. All rights reserved.
High-performance P-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions
(2003-02-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Lin, HN
;
Lu, CY
A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in, the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by, the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.
Fabrication and characterization of Schottky barrier polysilicon thin-film transistors with excimer-laser crystallized channel
(2003-04-01)
Yeh, KL
;
Lin, HC
;
Tsai, RW
;
Lee, MH
;
Huang, TY
Schottky barrier thin-film transistors (SB TFT) with field-induced drain (FID) have recently been demonstrated to exhibit ambipolar capability with low off-state leakage current. In this study, we investigate and compare the characteristics of poly-Si SB TFTs with channel layer prepared by excimer laser crystallization (ELC) and solid-phase crystallization (SPC). It is shown that the use of ELC could greatly improve the device characteristics, comparing to the SPC counterparts. Excellent device performance with steep subthreshold slope and on/off current ratio higher than 10(8) for both p- and n-channel operations are demonstrated on a single device with ELC channel. The effects of sub-gate bias, channel length, and channel offset length, on device characteristics are also explored.

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