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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performance
    (1998-12-01)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    Characteristics of plasma-enhanced chemical vapor deposited (PECVD) SiO2/SiNx passivation layers are modified to improve and optimize electrical performances such as program/erase cycle and hot carrier reliability of floating-gate nonvolatile memory devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics also correspond to increased program/erase cycles and lower % hot-carrier linear drain current (I-dlin) degradation An increase in RI from 1.520 to 1.675 translates to a rise in program/erase cycles from 17.3 K to 32 K and a fall in I-dlin from 8.2% to 4.9%. Further improvement in device performance is fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. Water diffusion from oxide and hydrogen release from nitride are both responsible for hot carrier drain current degradation and loss in program/erase cycles. The utilization of a high-RI oxide in conjunction with a low hydrogen content nitride would give rise to the optimal device reliability.
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    Charge pumping profiling technique for the evaluation of plasma-charging-enhanced hot-carrier effect in short-N-channel metal-oxide-semiconductor field-effect transistors
    (2002-07-01)
    Chen, SJ
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    Chung, SSS
    ;
    Lin, HC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Plasma etching of poly-silicon in a metal-oxide-semiconductor field-effect transistor (MOSFET) during the gate definition process induces edge damage at the gate-drain overlap edge. This edge damage will be further enhanced by the antenna effect and cause a more serious hot-carrier (HC) effect, particularly in short-channel devices. We call this phenomenon the plasma-charging-enhanced HC effect. In this paper, this plasma-charging-enhanced HC effect is evaluated by the charge pumping (CP) profiling technique, in which the enhanced damage at the gate-drain overlap gate oxide region can be identified. A three-phase plasma damage mechanism is then proposed to explain the observed effect. According to experimental results, it was shown that the interface traps generated at the gate-drain overlap edge are mainly attributed to the plasma-charging-enhanced HC effect. These interface traps (Nit) become the dominant mechanism of the drain current (ID) degradation, which increases with a reducing channel length (L). Again, the enhanced HC-effect-induced-degradation will dominate the device reliability under long-term operations.
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    Integration of modified plasma-enhanced chemical vapor deposited tetraethoxysilane intermetal dielectric and chemical-mechanical polishing processes for 0.35 mu m IC device reliability improvement
    (1997-09-01)
    Wang, YL
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    電子工程學系及電子研究所
    The process of interlevel dielectrics (ILD) between poly-Si and metal is critical to device characteristics and reliability. Also, the shrinking design rules demand greater hot carrier reliability, which is strongly influenced by the ILD process. In this paper we describe a process for improving the reliability of 0.35 mu m devices by using modified plasma-enhanced chemical vapor deposited tetraethoxysilane (PECVD-TEOS) N2O-rich or O-2-rich ILD films which contain less hydrogen concentration and excellent moisture resistance, and less mobile ion penetration after chemical-mechanical polishing (CMP), relative to standard PE-TEOS oxides. The hot carrier lifetime and the held isolation device threshold voltage are monitored and compared between devices with ILD layers based on different combinations of subatomespheric O-3-TEOS borophosphorus silicate glass (BPSG), standard PE-TEOS, O-2-rich and N2O-rich oxides. The material characteristics contributing to the reduction in post-CMP mobile ion levels and the improvement in device reliability will be discussed.