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Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
(2014-11-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance
(2010-10-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-mu m complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
(2010-11-01)
Yeh, Chih-Ting
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
(2000-04-01)
Ker, MD
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
On-chip ESD protection design by using polysilicon diodes in CMOS process
(2001-04-01)
Ker, MD
;
Chen, TY
;
Wang, TH
;
Wu, CY
;
電子工程學系及電子研究所
A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper, Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness, Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original similar to 300 V to become greater than or equal to3 kV, This design has been practically applied in a mass-production smart-card IC.
Extraction of eleven model parameters for consistent reproduction of lateral bipolar snapback high-current I-V characteristics in NMOS devices
(2001-06-01)
Chen, MJ
;
Lee, HS
;
Chen, ST
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A series of literature models originally devoted to the second breakdown trigger current I-t2 in a grounded-gate nMOS transistor can further find promising potential in handling high-current I-V due to lateral bipolar snapback. This is achieved primarily by building significant linkage between bipolar current-gain beta -related parameters: 1) the collector-to-base junction voltage dependencies A(1) and A(2) of the medium-level injection beta roll-off factor; 2) the high-level beta roll-off factor A(3); and 3) the collector-to-base junction voltage dependencies A(4) and A(5) Of the collector corner current at the onset of high-level beta roll-off. The new parameters A(1) to A(5) enable a consistent I-V solution along with other existing six model parameters such as the substrate resistance R-sub and its conductivity modulation factor A(r), the impact ionization coefficients K-1 and K-2, and the emitter series resistance R-e and collector series resistance R-c. Parameter extraction except Rc is thoroughly performed using only the parametric analyzer, and opposed to the traditional procedure, impact ionization coefficients and current gains are all assessed without entering the snapback regime. Remarkably, not only excellent agreements are gotten, but also bipolar snapback I-V measured under the current pulsing condition can be separated into two distinct parts: medium- and high-level injection region. This is quite effective under R-e = R-c. Series resistance, although having very low value, is not to be absent under the high-level injection conditions. Experimental evidences from test structures with different epitaxial layer thicknesses strongly confirm the validity of the assumptions such as R-e = R-c. In light of the epitaxial layer thickness dependencies of the model parameters, the epitaxial layer thickness effect is addressed as well.
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
(2008-05-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
電機學院
;
College of Electrical and Computer Engineering
The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (10). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
(2002-06-01)
Ker, MD
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using the thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35-mum CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 mum can be obviously improved from the original similar to2 kV to be greater than 8 kV by this SNTSCR device with a device dimension of only 60 mum/0.35 mum.
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
(2008-11-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mu m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
(2002-08-01)
Ker, MD
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original similar to2 kV to >8 kV by using this proposed ESD protection circuit.

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