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Design of Flip-Chip Interconnect Using Epoxy-Based Underfill Up to V-Band Frequencies With Excellent Reliability
(2010-08-01)
Hsu, Li-Han
;
Wu, Wei-Cheng
;
Chang, Edward Yi
;
Zirath, Herbert
;
Hu, Yin-Chu
This study demonstrates a flip-chip interconnect with epoxy-based underfill (epsilon(r) = 3.5 and tan delta = 0.02 at 10 MHz) for packaging applications up to V-band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al(2)O(3) substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip interconnect showed excellent performance from dc to 67 GHz with return loss below -20 dB and insertion loss less than 0.6 dB. Furthermore, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 degrees C/85 % relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the S-parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
(2000-09-01)
Jiang, IHR
;
Chang, YW
;
Jou, JY
;
資訊工程學系
;
電子工程學系及電子研究所
Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which ran optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstation.
Effect of aluminum seed layer on the crystallographic texture and electromigration resistance of physical vapor deposited copper interconnect
(2000-12-01)
Chin, YL
;
Chiou, BS
;
Wu, WF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of an Al underlayer with respect to texture control and electromigration (EM) resistance of Cu films are investigated in this study. The Al underlayer enhances the (111) texture of Cu films and the surface smoothness of the annealed Cu film. The same cubic crystal structure (face-centercd cubic) and small difference of the nearest interatomic distance of the (111) plane between Cu and Al result in the increase of the peak ratio I((111))/I-(200) of Cu films. The thicker the Al film, the more preferred the Cu (111) orientation. The resistivity of the Cu/AI bilayer film, which increases at about 0.2 mu Omega .cm per 1-nm-thick Al underlayer, is smaller than the reported value of single phase Cu(Al) solution. The EM resistance of Cu interconnects is also improved when the Al underlayer is present. The mean time to failure (MTF) of Cu interconnects with a 5-nm-thick Al underlayer is longer by one order of magnitude than that without an Al underlayer at 240 degreesC and 12 MA/cm(2).
Matching-based algorithm for FPGA channel segmentation design
(2001-06-01)
Chang, YW
;
Lin, JM
;
Wong, MDF
;
資訊工程學系
;
Department of Computer Science
Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the Literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis, In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multilevel matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work.
Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization design
(2001-12-01)
Lee, TGY
;
Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating the delay time of single line and coupled interconnect for ramp input waveform are derived, The accuracy of the signal delay time and crosstalk noise voltage models for various driver resistances, loading capacitances, and input-ramping rates has also been verified by simulation program with integrated circuit emphasis (SPICE) simulation. Based on the delay and crosstalk models, interconnect optimization design can be discussed thoroughly. The proposed guaranteed-performance interconnect design method is also discussed. These models are useful for performance estimation and layout optimization in VLSI synthesis as well as process optimization in technology development.
Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk models
(2001-12-01)
Lee, TGY
;
Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design.
Effect of the tantalum barrier layer on the electromigration and stress migration resistance of physical-vapor-deposited copper interconnect
(2002-05-01)
Chin, YL
;
Chiou, BS
;
Wu, WF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of a Ta barrier layer on electromigration and stress migration of Cu films are investigated. The Ta barrier layer enhances both the (111) texture and the median grain size of the annealed Cu films. At 225degreesC, the electromigration mean time to failure (225degreesC-MTF) of Ta/Cu/Ta multilayer interconnects is about two times longer than that of Cu monolayer interconnects. After 500 thermal cycles, the 225degreesC-MTF of Ta/Cu/Ta multilayer interconnects does not change and is about three times longer than that of Cu monolayer interconnects. The activation energy E-a of electromigration of Ta/Cu/Ta multilayer interconnects is 0.77 eV, which is higher than that of Cu monolayer interconnects (0.65 eV). Since the Ta/Cu/Ta specimen has enhanced crystallographic texture and larger grain size. it has both higher electromigration endurance and thermal stress resistance than Cu. However. the measured MTF is shorter than that predicted by an equation proposed by Vaidya and Sinha [Thin Solid Films 75 (1981) 253]. The shorter MTF and smaller E-a values for the Ta/Cu/Ta multilayer compared to the predicted ones are due to the weak Ta/Cu interface, A lifetime of 100 years is predicted for Ta/Cu/Ta multilayer interconnects with and without 500 thermal cycle stress.
Inductance modeling for on-chip interconnects
(2003-04-01)
Tu, SW
;
Shen, WZ
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Chang, YW
;
Chen, TC
;
Jou, JY
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout ( placement and routing) tool for inductance ( delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.
Effects of underlayer dielectric on the thermal characteristics and electromigration resistance of copper interconnect
(2003-12-01)
Chin, YL
;
Chiou, BS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of underlayer dielectric on the thermal characteristics and electromigration resistance of copper interconnects are investigated. It is shown that the thermal impedance of metal lines on polyimide is about three times that of metal lines on plasma-enhanced chemical vapor deposition of tetraethylorthosilicate (PETEOS) oxide. The open-circuit failure occurs after 75 s stressing at a current density of 1.4 x 10(7) A/cm(2) for polyimide underlayer specimens due to the high joule heating effect which causes the extreme temperature rise at, interconnects. Hence, decomposition of polyimide occurred which further accelerated the breakdown of interconnects. The thermal impedance is one of the major factors causing the electrical resistance to change during the electromigration (EM) test. The activation energies for electromigration of Cu are 0.87 eV for SiO2/Cu/PI2610 and 0.65 eV for SiO2/Cu/SiO2. After 500 thermal cycles, both the mean time-to-failure (MTF) and activation energy E-a decrease for EM, and lognormal standard deviation increases. At 225degreesC, the MTF of SiO2/Cu/PI2610 is about two times longer than that of SiO2/Cu/SiO2.
Electromigration in sputtered copper film on plasma-treated hydrogen silsesquioxane dielectric
(2004-04-01)
Chen, CT
;
Chiou, BS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electromigration (EM) damage is one of the major causes for the failure of interconnects. Plasma treatment, such as dry etching, is frequently employed in the fabrication of multilevel interconnection patterns. This work investigates the hydrogen silsesquioxane (HSQ) and copper integrated systems and the effect of H-2 plasma treatment on the EM of Cu. Hydrogen plasma bombardment induces a rough HSQ surface and results in a coarse morphology of the Cu film deposited on HSQ. The crystallographic texture of Cu is also affected by the plasma treatment. A decrease in the Cu I(111)/I(200) peak ratio is observed for a specimen treated with H-2 plasma. The activation energy for EM in Cu and the EM lifetime of the Cu interconnect decreases with an increased degree of plasma treatment. The activation energies obtained, ranging from 0.76 eV to 0.94 eV, suggest that the electromigration in copper proceeds via an interfacial diffusion path. Possible mechanisms for the effects of plasma treatment are explored. The rough surface and the retarded Cu (111) orientation induced by H-2 plasma bombardment are the major causes for the decrease of activation energy and EM lifetime.

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