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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
    (2013-02-01)
    Lin, Chun-Yu
    ;
    Tsai, Shiang-Yu
    ;
    Chu, Li-Wei
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.
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    Low-capacitance and fast turn-on SCR for RF ESD protection
    (2008-08-01)
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    Meng, Guo-Xuan
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESD-protected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well.
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    Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
    (2010-06-01)
    Yeh, Chih-Ting
    ;
    Ker, Ming-Dou
    ;
    Liang, Yung-Chih
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.