學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 11

Physics of Discrete Impurities under the Framework of Device Simulations for Nanostructure Devices
(2018-12-01)
Sano, Nobuyuki
;
Yoshida, Katsuhisa
;
Yao, Chih-Wei
;
Watanabe, Hiroshi
;
電機工程學系
Localized impurities doped in the semiconductor substrate of nanostructure devices play an essential role in understanding and resolving transport and variability issues in device characteristics. Modeling discrete impurities under the framework of device simulations is, therefore, an urgent need for reliable prediction of device performance via device simulations. In the present paper, we discuss the details of the physics associated with localized impurities in nanostructure devices, which are inherent, yet nontrivial, to any device simulation schemes: The physical interpretation and the role of electrostatic Coulomb potential in device simulations are clarified. We then show that a naive introduction of localized impurities into the Poisson equation leads to a logical inconsistency within the framework of the drift-diffusion simulations. We describe a systematic methodology for how to treat the Coulomb potential consistently with both the Poisson and current-continuity (transport) equations. The methodology is extended to the case of nanostructure devices so that the effects of the interface between different materials are taken into account.
次32奈米多重閘極元件的特性分析與模式建立---變異性與微縮性，高頻類比特性，以及介觀現象的探討
(2008)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在這個計畫中我們對次32 奈米多重閘極SOI CMOS 的元件特性作深入探討及模型建立。在工作項目一中，我們將建立一個適用於不同buried oxide 厚度的多重閘極SOI 元件的理論架構，我們的理論計算將涵蓋量子力學及原子等級的效應。我們的模型可用來預測次32 奈米多重閘極SOI 元件的電性變異及其可微縮性，將有助於多重閘極元件的設計。在工作項目二中，我們將綜合探討採用不同製程模組的多重閘極SOI 元件的高頻及類比特性。本研究可用來初步評估多重閘極SOI CMOS 技術在高頻及類比應用的發展潛力。在工作項目三中，我們將探討極小尺寸多重閘極元件的介觀現象。本研究對於瞭解次32 奈米多重閘極 SOI 電晶體的載子傳輸特性十分重要。
前瞻矽奈米元件變異性及傳輸特性綜合研究(I)
(2009)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載子傳輸特性，進行綜合研究。在工作項目一中，我們將分別對超薄基體(UTB)，多閘極(multi-gate)以及gate-all-around 奈米線金氧半場效電晶體，建立一套包含Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子效應的解析解模型，我們將研究這三種元件結構並搭配不同的通道材料，其對製程變異的敏感度。我們的元件模型也將有助於未來奈米級元件的設計。在工作項目二中，我們將廣泛地研究先進CMOS 場效電晶體的隨機不匹配特性(random mismatch)。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助於對奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在工作項目三中，我們將對奈米級應變矽元件的戴子傳輸特性進行研究。這項研究將有助於了解極微縮應變矽元件的戴子傳輸機制，也對未來提昇戴子遷移率的元件設計有所幫助。
前瞻矽奈米元件變異性及傳輸特性綜合研究(II)
(2010)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載子傳輸特性進行綜合研究。在工作項目一中，我們將分別對超薄基體(ultra-thin-body)，多閘極(multi-gate)以及環閘極(gate-all-around)金氧半場效電晶體，建立一套包含 Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子侷限效應的解析解模型，我們將研究這三種元件結構對製程變異的敏感度。我們的元件模型也將有助於未來奈米級元件的設計。在工作項目二中，我們將廣泛地研究奈米CMOS 場效電晶體的隨機不匹配特性。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助於對奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在工作項目三中，我們將對奈米CMOS 的戴子傳輸特性進行研究。這項研究將有助於了解極微縮奈米元件的戴子傳輸機制，也對未來提昇戴子遷移率的元件設計有所幫助。
Simulation and Investigation of Random Grain-Boundary-Induced Variabilities for Stackable NAND Flash Using 3-D Voronoi Grain Patterns
(2014-04-01)
Yang, Ching-Wei
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief investigates the random grain-boundary (GB)-induced variability in poly-crystalline silicon thin-film transistor for stackable NAND flash applications using 3-D Voronoi grain patterns. Compared with the 1-D and 2-D methods, the 3-D Voronoi grain can show a more realistic threshold-voltage variability when devices are downscaled along the channel height (Hch) direction. Therefore, a full 3-D consideration is needed when modeling the random GB-induced variation.
Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
(2013-07-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (V-th) design. Our results indicate that UTB SOI 6T SRAM cell using low V-th devices (vertical bar V-th vertical bar=0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in sigma RSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in sigma WSNM as comparaed with the case using higher V-th devices (vertical bar V-th vertical bar = 0.49 V). As V-th decreases (work function moves to the band edge), the "cell" access time improves significantly with correspondingly higher standby leakage. For low V-th devices (vertical bar V-th vertical bar = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower V-th devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications.
Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
(2013-06-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nein
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of a single acceptor-type and donor-type interface trap induced random telegraph noise (RTN) on tunnel FET (TFET) devices and its interaction with work function variation (WFV) using atomistic 3-D TCAD simulations. Significant RTN amplitude (Delta I-D/I-D) is observed for a single acceptor trap near the tunneling junction, whereas a donor trap is found to cause more severe impact over a broader region across the channel region. In addition, several device design parameters that can be used to improve TFET subthreshold characteristics (thinner equivalent oxide thickness or longer L-eff) are found to increase the susceptibility to RTN. Our results indicate that under WFV, TFET exhibits weaker correlation between I-ON and I-OFF than that in the conventional MOSFET counterpart. In the presence of WFV, the RTN amplitude can be enhanced or reduced depending on the type of the trap and the composition/orientation of metal-gate grain.
Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
(2013-01-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications.
Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi Approach
(2013-04-01)
Chou, Shao-Heng
;
Fan, Ming-Long
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Using a novel Voronoi method that can provide a more realistic representation of metal-gate granularity, we investigate and compare the impact of work-function variation (WFV) on FinFET and ultrathin body (UTB) silicon-on-insulator (SOI) devices. Our study indicates that, for a given electrostatic integrity and total effective gate area, the FinFET device exhibits better immunity to WFV than its UTB SOI counterpart. We further show that, unlike other sources of random variation, the WFV cannot be suppressed by equivalent oxide thickness scaling.
FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics
(2011-03-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Hsieh, Chien-Yu
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread, 0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite, 0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-k metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread, 0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO(2) and SiO(2)/HfO(2)) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the mu/sigma ratio in RSNM.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results