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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Subject: search.filters.subject.1T1R

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    Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
    (2018-10-01)
    Wang, Zhuo-Rui
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    Li, Yi
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    Su, Yu-Ting
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    Zhou, Ya-Xiong
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    Cheng, Long
    In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.
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    Reducing Forming Voltage by Applying Bipolar Incremental Step Pulse Programming in a 1T1R Structure Resistance Random Access Memory
    (2018-06-01)
    Zheng, Hao-Xuan
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    Chang, Ting-Chang
    ;
    Xue, Kan-Hao
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    Su, Yu-Ting
    ;
    Wu, Cheng-Hsien
    This letter introduces a method of using bipolarity bias voltages in the forming process to effectively reduce the forming voltage of a one-transistor and one-resistance random access memory device. A bipolar incremental-step-pulse programming process is applied, and a complete operation pulse for the forming process is described. This method reduces forming voltage without any cost to the device performance, and the device maintains good reliability. The likely physical mechanism of this bipolar operation is also presented based on the measured electrical characteristics.
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    新穎透明電阻式記憶體元件於高密度與低功率消耗的非揮發性記憶體應用
    (2015)
    曾俊元
    ;
    TSENG TSEUNG-YUEN
    ;
    國立交通大學電子工程學系及電子研究所
    隨著近年來消費性電子產品，如：智慧型手機、智慧型平面顯示器、筆記型電腦、MP3 和數位相機等，需求與日俱增，非揮發性記憶體已成為現今半導體工業研發重點之一。其中電阻式記憶體元件具結構簡單、元件尺寸小、低功率消耗與操作速度快速等特點，極有可能取代現今主流的快閃式記憶體(Flash Memory)，相當具有潛力成為下世代具三維度立體堆疊結構的高元件密度的非揮發性記憶體。為了整合平面顯示器與記憶元件於玻璃基板達到系統面板(system on panel：SOP)的目標，具透明結構的記憶體元件與周邊電路的研究，是非常急迫且重要的課題。因此本計畫的構想是以高密度與低功率的透明電阻式記憶體元件為基礎，利用本研究團隊既有的場效電晶體搭配電阻式記憶體結構(1T1R)與氧化物二極體搭配電阻式記憶體結構(1D1R)製造技術，進行元件奈米結構與三維度積體電路(3D-IC)應用的研究。 在此三年計畫中，第一年計畫主要工作為透明電阻式記憶體元件之製作，利用高度次序與高密度的氧化鋅(ZnO)奈米線薄膜結構與其他透明氧化物材料當作電阻轉態層來提升元件的記憶體特性，搭配不同的透明電極材料，製作於矽基板、玻璃基板、石英基板與可撓曲的塑膠基板上，研究探討不同透明電極材料組合之電阻式記憶體的電阻轉態機制與材料特性相依性。第二年計畫將根據本實驗室先前所發表的1T1R與1D1R技術，配合第一年研究的最佳化條件透明電阻式記憶體為基礎，探討1T1R與1D1R結構之整體電性影響。另外，製作具交叉條狀(Cross-bar)結構的透明電阻式記憶體陣列(Array)，進行陣列操作機制、透光率與撓曲率的研究。在第三年的研究中，將整合1T1R與1D1R的結構，搭配不同層數的交叉條狀記憶陣列，達到垂直延伸，高元件密度的三維度積體電路結構，進行記憶體特性效能與可靠度(Reliability)的測試。