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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Subject: search.filters.subject.Balun

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Now showing 1 - 8 of 8
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    A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
    (2011)
    Yang, Kai-Hsiang
    ;
    Kuo, Ming-Ching
    ;
    Yan, Tzu-Chao
    ;
    Kuo, Chien-Nan
    ;
    電子工程學系及電子研究所
    In this work, a balun low-noise amplifier (LNA) is designed and implemented in 0.18-mu m CMOS process. The bulk cross-coupling (BCC) and capacitance cross-coupling (CCC) techniques are introduced in this LNA, which not only increase gain and linearity but also decrease noise figure. The 3 dB bandwidth extends from 1.27 GHz to 5.31 GHz. The maximum differential gain is 10.13 dB. Measured at 3 GHz, P-1dB and IIP3 are -10 dBm and 0 dBm, respectively. The LNA core circuit dissipates 7.32 mW from 1.8 V power supply.
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    寬頻微波接取技術---子計畫三：關鍵寬頻矽製程單晶微波積體電路
    (2008)
    孟慶宗
    ;
    MENG CHINCHUN
    ;
    國立交通大學電信工程學系(所)
    隨著通訊技術的日新月異，及人們對於通訊資料量的要求，無線通訊系統的資料頻 寬也隨之越來越寬。目前，為了滿足高資料量的需求，寬頻技術通信運用也應運而生， 其涵蓋頻段必須足夠大。由於SiGe HBT 的高電流截止頻率(fT)，相當適合製作寬頻的射 頻電路。我們首先著手進行SiGe BiCMOS 寬頻射頻傳收器中關鍵零組件的研究，最後實 作出寬頻的傳收機。 我們在第一年將針對SiGe 寬頻低雜訊放大器(LNA)、振盪器(Oscillator)及集總積 體電路巴侖(balun)做研究。低雜訊放大器部分將首先由SiGe 元件分析著手，如此一來 可以進一步最佳化雜訊指數，振盪器部份則以正交相位振盪器為主。第二年將研究寬頻 操作的混頻器(Mixer)，我們將綜合使用微小化積體電路Marchand balun 來使得混頻器 的LO 輸入級達到寬頻的目的。在升頻混頻器的部分，我們可以使用多組LC current combiner 在RF 輸出端使其頻寬拉大，達到寬頻的要求。在第三年中，將整合設計寬頻 操作的射頻積體電路收發機。為了涵蓋多頻率範圍，多頻段頻率產生器將結合利用除頻 器及乘法器來實現。整個傳收機將基於前兩年所建立的子電路來組合出射頻收發機。 計畫工作內容如下： 第一年：寬頻SiGe 低雜訊放大器、震盪器和微小化集總積體電路巴侖之研究 第二年：SiGe 升頻降頻混頻器及結合寬頻Marchand balun 積體電路之研究 第三年：頻率最佳化及規劃、涵蓋多頻率範圍的多頻段頻率產生器、寬頻SiGe 射頻接 收機和傳送機積體電路。
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    Item type:Item,
    寬頻微波接取技術---子計畫三：關鍵寬頻矽製程單晶微波積體電路
    (2006)
    孟慶宗
    ;
    MENG CHINCHUN
    ;
    交通大學電信工程系
    隨著通訊技術的日新月異，及人們對於通訊資料量的要求，無線通訊系統的資料頻 寬也隨之越來越寬。目前，為了滿足高資料量的需求，寬頻技術通信運用也應運而生， 其涵蓋頻段必須足夠大。由於SiGe HBT 的高電流截止頻率(fT)，相當適合製作寬頻的射 頻電路。我們首先著手進行SiGe BiCMOS 寬頻射頻傳收器中關鍵零組件的研究，最後實 作出寬頻的傳收機。 我們在第一年將針對SiGe 寬頻低雜訊放大器(LNA)、振盪器(Oscillator)及集總積 體電路巴侖(balun)做研究。低雜訊放大器部分將首先由SiGe 元件分析著手，如此一來 可以進一步最佳化雜訊指數，振盪器部份則以正交相位振盪器為主。第二年將研究寬頻 操作的混頻器(Mixer)，我們將綜合使用微小化積體電路Marchand balun 來使得混頻器 的LO 輸入級達到寬頻的目的。在升頻混頻器的部分，我們可以使用多組LC current combiner 在RF 輸出端使其頻寬拉大，達到寬頻的要求。在第三年中，將整合設計寬頻 操作的射頻積體電路收發機。為了涵蓋多頻率範圍，多頻段頻率產生器將結合利用除頻 器及乘法器來實現。整個傳收機將基於前兩年所建立的子電路來組合出射頻收發機。 計畫工作內容如下： 第一年：寬頻SiGe 低雜訊放大器、震盪器和微小化集總積體電路巴侖之研究 第二年：SiGe 升頻降頻混頻器及結合寬頻Marchand balun 積體電路之研究 第三年：頻率最佳化及規劃、涵蓋多頻率範圍的多頻段頻率產生器、寬頻SiGe 射頻接 收機和傳送機積體電路。
  • Thumbnail Image
    Item type:Item,
    寬頻微波接取技術---子計畫三：關鍵寬頻矽製程單晶微波積體電路
    (2007)
    孟慶宗
    ;
    MENG CHINCHUN
    ;
    國立交通大學電信工程學系(所)
    隨著通訊技術的日新月異，及人們對於通訊資料量的要求，無線通訊系統的資料頻 寬也隨之越來越寬。目前，為了滿足高資料量的需求，寬頻技術通信運用也應運而生， 其涵蓋頻段必須足夠大。由於SiGe HBT 的高電流截止頻率(fT)，相當適合製作寬頻的射 頻電路。我們首先著手進行SiGe BiCMOS 寬頻射頻傳收器中關鍵零組件的研究，最後實 作出寬頻的傳收機。 我們在第一年將針對SiGe 寬頻低雜訊放大器(LNA)、振盪器(Oscillator)及集總積 體電路巴侖(balun)做研究。低雜訊放大器部分將首先由SiGe 元件分析著手，如此一來 可以進一步最佳化雜訊指數，振盪器部份則以正交相位振盪器為主。第二年將研究寬頻 操作的混頻器(Mixer)，我們將綜合使用微小化積體電路Marchand balun 來使得混頻器 的LO 輸入級達到寬頻的目的。在升頻混頻器的部分，我們可以使用多組LC current combiner 在RF 輸出端使其頻寬拉大，達到寬頻的要求。在第三年中，將整合設計寬頻 操作的射頻積體電路收發機。為了涵蓋多頻率範圍，多頻段頻率產生器將結合利用除頻 器及乘法器來實現。整個傳收機將基於前兩年所建立的子電路來組合出射頻收發機。 計畫工作內容如下： 第一年：寬頻SiGe 低雜訊放大器、震盪器和微小化集總積體電路巴侖之研究 第二年：SiGe 升頻降頻混頻器及結合寬頻Marchand balun 積體電路之研究 第三年：頻率最佳化及規劃、涵蓋多頻率範圍的多頻段頻率產生器、寬頻SiGe 射頻接 收機和傳送機積體電路。
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    A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique
    (2011-06-01)
    Li, Chun-Hsing
    ;
    Liu, Yen-Lin
    ;
    Kuo, Chien-Nan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this study, a low-power and low-voltage 5.5-GHz receiver front-end circuit is designed using a resonator coupling technique. An on-chip transformer combined with the parasitic capacitances from a low-noise amplifier (LNA), a mixer, and the transformer itself comprises two coupled resonators of the resonator coupling network (RCN). The RCN functions as a balun, and couples energy from the LNA to the mixer. Under the critical coupling condition, the RCN gives a maximal current gain at resonance frequencies, equivalent to the same level by an ideal transformer. The analysis shows that the current gain is quite tolerable to the coupling coefficient variation, an advantageous feature for on-chip transformer design. The technique is verified by the receiver front-end in 0.18-mu m CMOS technology. The RCN possess a current gain as high as 12 dB at 5.5 GHz. The measured input return loss, conversion gain, and third-order intermodulation intercept point of the entire circuit are 16 dB, 17.4 dB, and -1.5 dBm, respectively. The noise figure is 7.8 dB at the IF frequency of 1 MHz. The power consumption is only 0.33 mW from a 0.6-V supply. The required local oscillator power is only -9.5 dBm. This receiver front-end successfully demonstrates the resonator coupling technique.
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    Realization of High-Order S-Plane Bandpass Marchand Balun with No Lumped Elements
    (2012)
    Lin, Yun-Wei
    ;
    Chang, Chi-Yang
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    A high-order wideband planar balun is proposed in this paper. The balun is exactly synthesized using Richards' Theorem. Applying the S-plane bandpass other than high-pass prototype can shrink the circuit size and improve the stopband performance. Using the step impedance transformation, the proposed balun can be easily implemented in planar structure without lumped elements to fit the user-defined specification. A high-order balun with bandwidth about 100% and reflection level of -20dB is designed as an example. The simulation and measurement results are matched well.
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    A Filtering Microstrip Antenna Array
    (2011-11-01)
    Lin, Chin-Kai
    ;
    Chung, Shyh-Jong
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    A new filtering microstrip antenna array is presented. The antenna elements, together with the very compact feeding network, function as a third-order bandpass filter. The feeding network, which consists of one power divider and two baluns, provides the first two stages, and the microstrip antenna elements provide the last stage in the filter design. The equivalent lumped circuit model is analyzed, and the detail synthesis procedure is presented. A third-order filtering 2 x 2 microstrip antenna array is designed at a center frequency of 5 GHz with 3% fractional bandwidth and Chebyshev 0.3-dB equal-ripple broadside antenna gain response. The results from circuit model, full-wave simulation, and measurements agree well. Compared to the conventional patch antenna array, the proposed filtering microstrip antenna array successfully suppresses the unwanted signals in out-of-band, preserves good selectivity at band edges, and retains the flatness of the pass-band broadside antenna gain response.
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    A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 mu m CMOS
    (2009-03-01)
    Kuo, Ming-Ching
    ;
    Kao, Shiau-Wen
    ;
    Chen, Chih-Hung
    ;
    Hung, Tsun-Shuen
    ;
    Shih, Yi-Shing
    A fully integrated direct-conversion tuner is implemented in 0.13 mu m CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L-bands, and occupies only 7.2 mm(2) die area.