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Subject: search.filters.subject.Characteristic fluctuation

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Now showing 1 - 8 of 8
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    Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps
    (2020-03-01)
    Kola, Sekhar Reddy
    ;
    Li, Miming
    ;
    Thoti, Narasimhulu
    ;
    交大名義發表
    ;
    電機工程學系
    The random telegraph noise (RTN) in gate-all-around (GAA) silicon (Si) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) induced by a single charge trap (SCT) or random interface traps (RITs) is studied for the first time. An experimentally validated three-dimensional quantum-mechanically-corrected device simulation is advanced to investigate the explored devices. The magnitude of the RTN decreases with increasing gate voltage to different extents for the planar MOSFET, bulk FinFET, and GAA Si NW MOSFET devices, owing to the reduction in the conducting carriers along the channel. For the GAA Si NW MOSFET, the reduction of the fluctuation of threshold voltage in the presence of RITs is about 25 and 3 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 6 and 2.6 times, respectively. For the GAA Si NW MOSFET, the reduction of the RTN in the presence of RITs is about 7.5 and 4.7 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 22 and 6 times, respectively. At given threshold voltage, compared with the results for the planar MOSFETs and bulk FinFET, the GAA Si NW MOSFET exhibits minimal characteristic variability and RTN owing to the ultimate electrostatic control of the gate from the point of view of electrostatic integrity.
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    Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants
    (2015-03-11)
    Huang, Wen-Tsung
    ;
    Li, Yiming
    ;
    電機工程學系
    ;
    電信工程研究所
    ;
    Department of Electrical and Computer Engineering
    In this work, we use an experimentally calibrated 3D quantum mechanically corrected device simulation to study the random dopant fluctuation (RDF) on DC characteristics of 16-nm-gate trapezoidal bulk fin-type field effect transistor (FinFET) devices. The fixed top-fin width, which is consistent with the realistic process by lithography, of trapezoidal bulk FinFET devices is considered in this study. For RDF on trapezoidal bulk FinFETs under the fixed top-fin width, we explore the impact of geometry and RDF on the on-/off-state current and the threshold voltage (V-th) fluctuation with respect to different channel fin angles. For the same channel doping concentration, compared with an ideal FinFET (i.e., device with a right angle of channel fin), the off-state current is large in trapezoidal bulk FinFETs with a small fin angle. Furthermore, the short-channel effect and V-th variation degrade as the fin angle is getting smaller. The magnitude of the normalized sigma V-th increases 7% when the fin angle decreases from 90 degrees to 70 degrees.
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    DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs
    (2018-06-01)
    Sung, Wen-Li
    ;
    Li, Yiming
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal-oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage (Vth) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of Vth. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process.
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    16奈米矽多重閘極電晶體中隨機摻雜導致之特性擾動及其抑制方法
    (2008)
    李義明
    ;
    LI YIMING
    ;
    國立交通大學電信工程學系(所)
    隨著矽製程技術的演進，超大型積體電路元件已進入次45 奈米生產技術，除了傳統製程變異效應，隨機摻雜問題所造成的擾動已嚴重的影響了場效應電晶體的特性與可靠度。在去年的計畫中 (隨機摻雜在次20 奈米矽場效應電晶體特性擾動之研究)，吾人已成功地以實驗與理論分析次20 奈米矽場效應電晶體特性之擾動，研究指出20 奈米電晶體臨界電壓的隨機摻雜擾動將高達40 mV，此模擬結果與台積電的實際量測結果(39 mV)非常吻合，此結果已陸續發表於2007年VLSI會議以及IEEE相關期刊。 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點，新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案；其中，20 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢，因此研究隨機摻雜問題在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。延續先前計畫所開發之模擬分析方法，本計劃將以兩年之時間完整研究隨機摻雜在16奈米等級多閘極立體場效應電晶體導致的擾動問題及其抑制方法；第一年計畫將結合實驗與理論研究含平面SOI電晶體、雙閘極電晶體、三閘極SOI電晶體、三閘極塊材電晶體、方塊全閘極電晶體、圓形全閘極電晶體、類圓形全閘極電晶體，…等立體元件隨機摻雜導致的電特性擾動，其中關於閘極長度暨製程線寬變化導致的擾動也將一起分析。同時為了壓抑次20 奈米元件中高達40 mV 以上的臨界電壓擾動，吾人於第二年計畫將針對上述的平面與多閘極立體電晶體，在兼具高性能電特性要求之前提下，找尋壓抑擾動之物理機制並從材料與製程之觀點提出有效壓抑擾動的方法，如：摻雜分布之最佳化、閘極工程與閘極高介電材料的使用，…等等，並與台積電進行實驗驗證與製程最佳化。最後根據所研究之壓抑擾動的物理機制與實驗數據，推演能準確描述隨機摻雜導致電特性擾動的解析公式。
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    16奈米矽多重閘極電晶體中隨機摻雜導致之特性擾動及其抑制方法
    (2009)
    李義明
    ;
    LI YIMING
    ;
    國立交通大學電信工程學系(所)
    隨著矽製程技術的演進，超大型積體電路元件已進入次45 奈米生產技術，除了傳統製程變異效應，隨機摻雜問題所造成的擾動已嚴重的影響了場效應電晶體的特性與可靠度。在去年的計畫中 (隨機摻雜在次20 奈米矽場效應電晶體特性擾動之研究)，吾人已成功地以實驗與理論分析次20 奈米矽場效應電晶體特性之擾動，研究指出20 奈米電晶體臨界電壓的隨機摻雜擾動將高達40 mV，此模擬結果與台積電的實際量測結果(39 mV)非常吻合，此結果已陸續發表於2007年VLSI會議以及IEEE相關期刊。 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點，新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案；其中，20 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢，因此研究隨機摻雜問題在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。延續先前計畫所開發之模擬分析方法，本計劃將以兩年之時間完整研究隨機摻雜在16奈米等級多閘極立體場效應電晶體導致的擾動問題及其抑制方法；第一年計畫將結合實驗與理論研究含平面SOI電晶體、雙閘極電晶體、三閘極SOI電晶體、三閘極塊材電晶體、方塊全閘極電晶體、圓形全閘極電晶體、類圓形全閘極電晶體，…等立體元件隨機摻雜導致的電特性擾動，其中關於閘極長度暨製程線寬變化導致的擾動也將一起分析。同時為了壓抑次20 奈米元件中高達40 mV 以上的臨界電壓擾動，吾人於第二年計畫將針對上述的平面與多閘極立體電晶體，在兼具高性能電特性要求之前提下，找尋壓抑擾動之物理機制並從材料與製程之觀點提出有效壓抑擾動的方法，如：摻雜分布之最佳化、閘極工程與閘極高介電材料的使用，…等等，並與台積電進行實驗驗證與製程最佳化。最後根據所研究之壓抑擾動的物理機制與實驗數據，推演能準確描述隨機摻雜導致電特性擾動的解析公式。
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    The intrinsic parameter fluctuation on high-kappa/metal gate bulk FinFET devices
    (2013-09-01)
    Li, Yiming
    ;
    Su, Hsin-Wen
    ;
    Chen, Yu-Yu
    ;
    Hsu, Sheng-Chia
    ;
    Huang, Wen-Tsung
    In this work, based on the experimentally calibrated 3D device simulation, we for the first time estimate the impact of intrinsic parameter fluctuation on the electrical characteristic of 16-nm-gate TiN/HfO2 bulk FinFETs. The sources of intrinsic parameter fluctuation include the random discrete dopants, interface traps and work function differences, simultaneously. The full 3D simulated threshold voltage fluctuation, induced by the aforementioned random sources simultaneously, is 26.2 mV for the N-type bulk FinFET (and is 55.5 mV for the planar N-MOSFET). For the N-type bulk FinFE'T, the statistical sum of these fluctuations is 9.5% (and is 12.3% for the planar device) overestimation, compared with the full 3D simulation. One of the main reasons is the independence assumption on these random variables is destroyed owing to interactions to different extents among RDs, ITs and WKs. The coupled surface potentials cannot be simply estimated by using their statistical sum of individual random source. Under the same threshold voltage, compared with the result of the planar MOSFETs, more than 50% reduction on the threshold voltage fluctuation of the explored bulk FinFETs is observed owing to the benefit of 3D structural nature. (C) 2013 Elsevier B.V. All rights reserved.
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    High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants
    (2008-12-01)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations in the large-scale statistically sound "atomistic" device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7% variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4% variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFET's surface to substrate is further performed to examine the associated fluctuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctuations of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced intrinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit.
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    Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits
    (2009-08-01)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Li, Tien-Yeh
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function-and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale CMOS field-effect-transistor circuits.