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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 10 of 32

A Low-Cost Wear-Leveling Algorithm for Block-Mapping Solid-State Disks
(2011-01-01)
Chang, Li-Pin
;
Huang, Li-Chun
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資訊工程學系
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Department of Computer Science
Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wear-leveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
(2010-10-01)
Chang, Li-Pin
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資訊工程學系
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Department of Computer Science
Replacing power-hungry disks with NAND-flash-based solid-state disks (SSDs) is a recently emerging trend in flash-memory applications. One important SSD design issue is achieving a good balance between cost, performance, and lifetime. This study introduces a hybrid approach to large SSDs that combines MLC NAND flash and SLC NAND flash. Each of these flash architectures has its own drawbacks and benefits, and this study proposes that the two can complement each other. However, there are technical challenges pertaining to data placement, data migration, and wear leveling in heterogeneous NAND flash. The experimental results of our study show that combining 256 MB SLC flash with 20 GB MLC flash produces a hybrid SSD. This hybrid SSD is 1.8 times faster than a purely MLC-flash-based SSD in terms of average response time and improves energy consumption by 46 percent. The proposed hybrid SSD costs only four percent more than a purely MLC-flash-based SSD. The extra cost of a hybrid SSD is very limited and rewarding.
Lightweight Data Compression for Mobile Flash Storage
(2017-10-01)
Ji, Cheng
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Chang, Li-Pin
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Shi, Liang
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Gao, Congming
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Wu, Chao
Data compression is beneficial to flash storage lifespan. However, because the design of mobile flash storage is highly cost-sensitive, hardware compression becomes a less attractive option. This study investigates the feasibility of data compression on mobile flash storage. It first characterizes data compressibility based on mobile apps, and the analysis shows that write traffic bound for mobile storage volumes is highly compressible. Based on this finding, a lightweight approach is introduced for firmware-based data compression in mobile flash storage. The controller and flash module work in a pipelined fashion to hide the data compression overhead. Together with this pipelined design, the proposed approach selectively compresses incoming data of high compressibility, while leaving data of low compressibility to a compression-aware garbage collector. Experimental results show that our approach greatly reduced the frequency of block erase by 50.5% compared to uncompressed flash storage. Compared to unconditional data compression, our approach improved the write latency by 10.4% at a marginal cost of 4% more block erase operations.
HfO2 Trap Layer Nonvolatile Flash Memory on SiGe Channel
(2014-01-01)
Lin, Yu-Hsein
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Li, Jyun-Han
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You, Hsin-Chiang
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Hong, Jin-Shi
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Tsai, Wan-Ting
This paper study a novel nonvolatile memory by using HfO2 trapping layer on epi-SiGe (Ge: 15%) channel. Because SiGe has a smaller bandgap than that of silicon, it can increases the electron/hole injection and enhances the program/erase speed. This study compares the characteristics of HfO2 memories with different tunnel oxynitride thicknesses on epi-SiGe substrate. The results show that the nonvolatile memory has superior characteristics in terms of considerably large memory window, high speed program/erase, long retention time, good endurance for future low power applications.
A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells
(2015-08-01)
Wang, Pei-Yu
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Tsui, Bing-Yue
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (V-T) induced by the discrete grain-boundary traps are studied. Various Delta V-T behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Delta V-T is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of V-T in 3-D VG memory cells.
New Accurate Method to Analyze both Floating Gate Charge and Tunnel Oxide Trapped Charge Profile in NAND Flash Memory
(2014-01-01)
Shirota, R.
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Yang, B-J.
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Chiu, Y-Y
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Chen, H-T.
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Ng, S-F.
New method to extract the amount of floating (FG) charge (Q(FG)) apart from oxide trapped charge (Q(OX)) generated by program and erase (P/E) cycles is proposed, for the first time. Q(FG) shift by P/E cycling shows asymmetry between programmed and erased states as follows; vertical bar Q(FG)vertical bar exhibits the peak at similar to 100 cycles in programmed state, while vertical bar Q(FG)vertical bar monotonically reduces in erased state. Next, the midgap voltage (V-mid) shift of the cell caused by the generation of Q(OX) is also extracted by this method. Therefore, it enables to analyze the profiles of the hole and electron-trap separately across the oxide in detail. It is demonstrated that the hole-trap is mainly distributed near to Si surface and the centroid of electron-trap is located near to the middle of oxide. In addition, it is found that hole-trap near to Si has strong dependence on erase bias.
New Method to Analyze the Shift of Floating Gate Charge and Generated Tunnel Oxide Trapped Charge Profile in NAND Flash Memory by Program/Erase Endurance
(2015-01-01)
Shirota, Riichiro
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Yang, Bo-Jun
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Chiu, Yung-Yueh
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Chen, Hsuan-Tse
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Ng, Seng-Fei
A new test system was devised and used to separate the amount of floating gate (FG) charge (Q(FG)) from the oxide trapped charge (Q(OX)) generated by program-and-erase (P/E) cycles. We also extracted the pure V-mid shift caused by the generation of Q(OX), which is separated from the part of V-t shift coming from Q(FG) deviation. The identification of Q(FG) and Vmid shift makes it possible to analyze the detailed the oxide trapped charge profile. The Q(FG) shift generated by P/E cycles displays asymmetry between the programmed and erased states: the absolute value of Q(FG) exhibits a maximum at similar to 100 cycles in the programmed states, while Q(FG) monotonically decreases in the erased one. Considering that the Fowler-Nordheim tunneling current is sensitive to the oxide trap near the cathode, itself the source of electron tunneling current, our results indicate that the hole trap is dominant near to Si, whereas the electron trap is dominant near FG.
高速操作及高資料保存特性SONOS型式快閃記憶體之研究
(2008)
莊紹勳
;
Chung Steve S
;
國立交通大學電子工程學系及電子研究所
傳統的浮動閘極(floating gate) 快閃式記憶體，受限於資料保存(data retention)問題，穿隧氧化層(tunnel oxide)無法繼續微縮，SONOS 則具有可微縮性(scalability)、可以有較佳的資料保存、低電壓操作、適合箝入式(embedded)設計等優點。SONOS 結構快閃式記憶體的研究，在國內研究則相當缺乏，本計劃著眼於此，規劃三年時程的研究計劃，建立一套完整的SONOS Flash cell 架構，嘗試利用Nitride 介電層及金屬化合物電荷儲存層(charge storage)結構的SONOS-type 快閃式記憶體，以達到同時可以高速操作及較佳資料保存(dada retention)特性等優點，建立相關製程模組，並探討其漏電流機制及可靠性的分析方法。本計劃預期完成的工作有：第一年計劃工作的執行，我們將更改傳統 SONOS 中ONO layer 的設計，將ONO layer 改為Nitride 介電層/金屬化合物/Nitride(NMN)結構，以期達到可以高速操作、具高可靠性、較佳data retention 的SONOS 快閃式記憶體元件設計。主要工作包含：建立high-k nitride 做為tunnel oxide、成長高可靠性低漏電流tunnel oxide 技術、開發metal-storage node 材料，建立相關製程模組，以及各種不同tunnel nitride 結構、storage node 的各項性能(performance)及可靠性的研究。第二年主要是延續第一年的元件製作及各種操作模式，完成具體的可靠性評估，包含： Cell Endurance、Data retention 等的可靠性量測，元件在P/E cycling 以後，tunnel oxide 所造成氧化層傷害的可靠性量測方法研究及各項leakage current 模型建立，依第一年完成的不同的tunnel nitride、blocking nitride 厚度條件sample，研究出scaling 的設計準則。最後一年則是利用 metal-NC 技術取代前一年的電荷儲存層於SONOS cell 的製作，期能達到更好的data retention 的目標及操作速度、operation window、可靠性等的評估，建立一套利用metal-NC 技術於SONOS cell 製程與元件的設計準則。最後成果預期可以有世界級水準的論文發表，研究成果更可做為產業界下一世代快閃記憶體的重要參考。
用於快閃式記憶元件及電路性能與可靠性模擬的元件模式
(2000)
莊紹勳
;
Chung Steve S
;
交通大學電子工程系
先進低電壓低功率及高效能快閃式記憶體之研究(I)
(2001)
莊紹勳
;
Chung Steve S
;
交通大學電子工程系

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