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Subject: search.filters.subject.Ge

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Now showing 1 - 10 of 16
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    Feasibility of Ge double quantum dots with high symmetry and tunability in size and inter-dot spacing
    (2019-01-01)
    Peng, Kang-Ping
    ;
    Huang, Tsung-Lin
    ;
    George, Thomas
    ;
    Lin, Horng-Chih
    ;
    Li, Pei-Wen
    We report the tunability of the sizes and inter-dot spacings of Ge coupled quantum dots (QDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15. Spherical-shaped Ge QDs were formed at each sidewall corner of the nano-patterned Si3N4 ridges by thermal oxidation of poly-SiGe spacer layers encapsulating the Si3N4 nano-ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical height, width, and length of the nano-spacer islands of poly-SiGe, which are tunable by adjusting the process times of their deposition and etch back. The inter-dot spacing between the Ge DQDs are controllable by adjusting the widths of the lithographically-patterned Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD sizes as well as the coupling barriers between the QDs and external electrodes in close proximity.
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    Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform
    (2018-01-01)
    Liao, P. H.
    ;
    Kuo, M. H.
    ;
    Tien, C. W.
    ;
    Chang, Y. L.
    ;
    Hong, P. Y.
    We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5-90nm), SiO2 thickness (2-4nm), and Ge content (x = 0.65-0.85) and strain engineering (epsilon(comp) = 1-3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L-G of 75nm JL n-FETs feature I-ON/I-OFF > 5x10(8), I-ON > 500 mu A/mu m at V-DS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity > 1,000A/W and current gain linearity ranging from nW-mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300-1600nm (NUV-NIR) are observed on 5-100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.
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    Gate-First TaN/La2O3/SiO2/Ge n-MOSFETs Using Laser Annealing
    (2010-11-01)
    Chen, W. B.
    ;
    Wu, C. H.
    ;
    Shie, B. S.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    To improve device performance, laser annealing was applied to Ge n-MOSFETs, which gave a low sheet resistance of 68 Omega/sq, a small ideality factor of 1.3, and a large similar to 10(5) forward\reverse current in the source-drain n(+)/p junction. The laser-annealed gate-first TaN/La2O3/SiO2/Ge n-MOSFETs showed a high mobility of 603 cm(2)/Vs and a good mobility of 304 cm(2)/Vs at a 1.9-nm equivalent oxide thickness.
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    High-Performance Gate-First Epitaxial Ge n-MOSFETs on Si With LaAlO3 Gate Dielectrics
    (2010-12-01)
    Chen, W. B.
    ;
    Cheng, C. H.
    ;
    Chin, Albert
    ;
    光電學院
    ;
    電子工程學系及電子研究所
    This brief presents high-performance Ge n-MOSFETs with good high-field mobility of 218 cm(2)/V . s at 0.5 MV/cm, low subthreshold swing (SS) of 108 mV/dec, small equivalent oxide thickness (EOT) of 1.6 nm, low 7 x 10(-10) A/mu m OFF-state leakage, small bias temperature instability of 31 mV at 1.2 V overdrive and 85 degrees C, and full process compatibility with current very large-scale integration fabrication. These are one of the best SS and high-field mobility data among gate-first Ge n-MOSFETs using epitaxial Ge on 6-in Si wafer and proper high-kappa LaAlO3 dielectric without using an interfacial layer. Using a different high-kappa HfAlO gate dielectric, the Ge n-MOSFETs showed poor leakage, large flatband voltage shift, and degraded EOT.
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    High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
    (2010-01-01)
    Chen, W. B.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
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    High-Performance Charge-Trapping Flash Memory Device With an Ultrathin 2.5-nm Equivalent-Si3N4-Thickness Trapping Layer
    (2012-01-01)
    Tsai, C. Y.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We made the MoN-[SiO2-LaAlO3]-[Ge-HfON]-[LaAlO3-SiO2]-Si charge-trapping (CT) Flash device with a record-thinnest 2.5-nm equivalent-Si3N4-thickness trapping layer, a large 4.4-V initial memory window, a 3.2-V ten-year extrapolated retention window at 125 degrees C, and a 3.6-V endurance window at 106 cycles, under very fast 100 mu s and low +/- 16-V program/erase pulses. These were achieved using Ge reaction with a HfON trapping layer for better CT and retention.
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    Ultra-Low Power Green Electronic Devices
    (2015)
    Yi, S. H.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Power consumption is the crucial challenge for electronics. To lower the DC leakage power (P-DC), we applied the high-kappa gate dielectric to CMOS from the physics of Q equivalent to CV. More than 2 orders of magnitude lower P-DC is obtained at small 0.5 similar to 0.9 nm equivalent-oxide-thickness (EOT). The high-kappa dielectric also increases the charge controllability of flash memory and decrease the V-T disturbance by nearly cells, which improves cell density and cost. The AC power (P-AC) can be lowered by using high-mobility Ge CMOS at a lower V-D and 3D IC with a small capacitance, from basic physics of P-AC equivalent to CV(D)(2)f/2.
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    High Quality Ge Epitaxial Films Grown on In0.51Ga0.49P/GaAs and GaAs Substrates by Ultra High Vacuum Chemical Deposition
    (2014-01-01)
    Su, Yung-Hsuan
    ;
    Tang, Shih-Hsuan
    ;
    Nguyen, Chi Lang
    ;
    Kuan, Ching-Wen
    ;
    Yu, Hung-Wei
    The epitaxial growth of high quality Ge thin films on different materials of In0.51Ga0.49P and GaAs by ultra high vacuum chemical vapor deposition (UHVCVD) system was studied. The crystallinity of high quality Ge layers on In0.51Ga0.49P and GaAs layers can be proved by X-ray diffraction (XRD) and transmission electron microscopy (TEM). The comparison of surface morphology between Ge grown on In0.51Ga0.49P and GaAs was also analyzed by atomic force microscopy (AFM). The roughness of Ge on GaAs shows better than that of In0.51Ga0.49P. Both of these structures were designed for fabricating p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) for the integration of Ge p-channel device with III-V n-channel electronic device.
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    在矽基板整合40奈米三五族與鍺量子井場效電晶體作為低功率與高速無線之應用(I)
    (2009)
    張翼
    ;
    CHANG EDWARD YI
    ;
    國立交通大學材料科學與工程學系(所)
    矽半導體技術，發展至30 奈米已面臨瓶頸，需有高載子遷移率材料加入，以使技 術得以持續發展，三五量子井場效電晶體或稱調變摻雜場效電晶體為現今所知速度最快 之場效電晶體，具有高速、低功率特性，但因為三五族材料之低電洞遷移率使其無法製 作互補的結構，本計畫即利用高電洞遷移率鍺通道與高電子遷移率的三五材料透過矽鍺 緩衝層成長在矽晶片來解決此問題。 在本計畫，三五n 型元件將利用矽鍺與砷化銦鋁假晶緩衝層成長在矽基板，通道 將採用砷化銦鎵，n 型施體層將使用砷化銦鋁。P 型元件將會製作在釋放應力矽鍺緩衝 層，電洞提供層將使用矽、矽鍺或砷化鎵。 本研究將整合材料成長、新穎元件結構、元件製造技術、發展三五族鍺通道量子 井電晶體，作為發展新世代半導體技術，作為高速數位與超高頻寬微波連線應用。此 一元件將可應用在220 GHz 無線的通訊與光纎通信系統。此外本計畫發展之量子井元 件更可整合在22 奈米以下CMOS 技術作為低功率晶片無線互連之應用，將為下世代 晶片信號連結展開新的一頁。 施敏教授，張俊彥教授，美國英代爾半導體Dr. Robert Chau，日本工學大學Prof. Hiroshi Iwai 與瑞典查默爾大學Prof. Herbert Zirath 等世界知名專家將參與本學術卓越 計畫之執行及技術顧問。
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    Growth of high-quality Ge epitaxial layers on Si(100)
    (2003-05-15)
    Luo, GL
    ;
    Yang, TH
    ;
    Chang, EY
    ;
    Chang, CY
    ;
    Chao, KA
    A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum.