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Subject: search.filters.subject.LDPC

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Now showing 1 - 7 of 7
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    An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
    (2010-11-01)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology
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    A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications
    (2016-01-01)
    Lin, Chia-Lung
    ;
    Liu, Rong-Jie
    ;
    Chen, Chih-Lung
    ;
    Chang, Hsie-Chia
    ;
    Lee, Chen-Yi
    LDPC block codes (LDPC-BCs) have attracted great interests in recent years by highly parallel computation and good bit-error-rate performance, and one of the decoder implementation issues is high routing complexity. LDPC convolutional codes (LDPC-CCs) not only release routing complexity but also are natural to dynamic length of data frame. Thus, the codes are very suitable for video stream and pre-5G wireless communication systems. LDPC-CC decoder is composed of several concatenated processors, where the long FIFOs are usually the bottleneck of area and decoding latency. To improve hardware efficiency, we use overlapped architecture to share partial FIFO between processors. Furthermore, check node unit and hybrid-partitioned FIFO are proposed to increase throughput and pipeline efficiency. The measurement results of test chip in 65nm technology show that our work can achieves 7.72 Gb/s under 322MHz operating frequency. The decoder with 6 processors occupies an area of 1.19 mm(2), drawing 410.5 mW of power with an energy efficiency of 8.75pJ/bit/proc.
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    Item type:Item,
    An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
    (2010-11-01)
    Hung, Jui-Hui
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work a high performance LDPC decoder architecture is presented It is a partially parallel architecture for low complexity consideration In order to eliminate the idling time and hardware complexity in conventional partially parallel decoders the decoding process decoder architecture and memory structure are optimized Particularly the parity check matrix is optimally partitioned into four unequal sub matrices that lead to high efficiency in hardware sharing As a result it can handle two different codewords simultaneously with 100% hard ware utilization Furthermore for minimizing the performance loss due to round off errors in fixed point implementations the well known mod died min sum decoding algorithm is enhanced by our recently proposed high performance CMVP decoding algorithm Overall the proposed de coder has high throughput low complexity and good BER performances In the circuit implementation example of the (576 288) parity check matrix for IEEE 802 16e standard the decoder achieves a data rate of 5 5 Gbps assuming 10 decoding iterations and 7 quantization bits with a small area of 653K gates based on UMC 90 nm process technology
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    A systematic optimized comparison algorithm for LDPC decoder
    (2008)
    Hung, Jui-Hui
    ;
    Hung, Jui-Hung
    ;
    Chen, Sau-Gee
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper proposes a novel systematic optimized comparison algorithm for LDPC codes with arbitrary code lengths. Based on the presented algorithm, we also design a corresponding decoder architecture which has a short comparison delay time of [log(2)(n-1)] and a very low comparator complexity of n x [log(2) (n - 1)], where n is the input number to CNU. Besides, the proposed design is general, systematic and flexible, which can be applied to arbitrary input number of a CNU. The designed CNU is favorable to the existing CNU designs which are non-systematically designed with either longer critical path delays or higher comparator counts than the proposed designs. The proposed design is particularly good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design complexity.
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    A 11.5-Gbps LDPC Decoder Based on CP-PEG Code Construction
    (2009)
    Chen, Chih-Lung
    ;
    Lin, Kao-Shou
    ;
    Chang, Hsie-Chia
    ;
    Fang, Wai-Chi
    ;
    Lee, Chen-Yi
    In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.
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    An energy saving scheme for long range and high data rate wireless sensor networks
    (2007)
    Lin, Li-Hsieh
    ;
    Tsou, Wen-An
    ;
    Fan, Long-Sheng
    ;
    Wuen, Wen-Shen
    ;
    Wen, Kuei-Ann
    For increasing demands on transceiving coverage, reliability and high resolution of sensing data in modem wireless sensor network applications, a novel digital transceiver scheme for wireless sensor node with integration of WiMAX PHY QoS, and low-density parity check (LDPC) code had been proposed. It will be 67% energy saving to support high gain sensing amplifier thus to provide high resolution digitization of sensing data. With WiMAX based regulation, 30 mile transmission range and 74Mbps data rate for long range and high data rate wireless sensor networks can be achieved.