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Now showing 1 - 7 of 7

Normally-Off Tri-Gate GaN MIS-HEMTs with 0.76 m Omega center dot cm(2) Specific On-Resistance for Power Device Applications
(2019-08-01)
Wu, Chia-Hsun
;
Chen, Jian-You
;
Han, Ping-Cheng
;
Lee, Ming-Wen
;
Yang, Kun-Sheng
A GaN metal-insulator-semiconductor high electronmobility transistor (MIS-HEMT) using tri-gate architecture and hybrid ferroelectric charge trap gate stack is demonstrated for normally-off operation. Compared with the conventional planar device, the tri-gate device has the 2-D electron gas (2-DEG) channel exposed on the nanowire sidewalls, so that the trapped charges in the HfON charge-trapping layer can easily deplete the channel from the sidewalls, leading to a high positive threshold voltage (V-th) to realize the normally-off operation. Moreover, through this electrostatic control on the sidewall, a high density of negative charge caused by hybrid ferroelectric charge trap gate stack with the optimized tri-gate structure, the tri-gate device can achieve normally-off GaN device with both low on-resistance (R-ON) and high positive V-th. The designed tri-gate device exhibits a high V-th of +2.61 V at current density (I-DS) = 1 mu A/mm, a high maximum current density (I-DS, MAX) of 896 mA/mm, a low R-ON of 5.0 Omega center dot mm and a high breakdown voltage (BV) of 788 V. To the best of our knowledge, the proposed tri-gate device shows the lowest specific on-resistance (R-ON,R- SP) among reported normallyoff GaN device results with BV > 650 V.
Investigation of Degradation Phenomena in GaN-on-Si Power MIS-HEMTs under Source Current and Drain Bias Stresses
(2018-01-01)
Yang, Chih-Yi
;
Wu, Tian-Li
;
Hsieh, Tin-En
;
Chang, Edward Yi
;
材料科學與工程學系
In this paper, we investigate the degradation phenomena in GaN-on-Si Metal-Insulator-Semiconductor High electron Mobility Transistors (MIS-HEMTs) in the cascode topography for enhancement mode power switching applications. Different stress conditions, e.g., constant source current (Is=100(mu A)=2(mA/mm) and 100(nA)=2 x 10(-3)(mA/mm)) and drain voltages (V-D=1(V), 10(V), 100(V), and 200(V)), are used to investigate the source current and drain bias dependent degradation. First, the VTH shift is correlated with the RoN increase under a low drain bias stress (V-D<10(V)). However, under a high drain bias stress, the trapping location is most probably in the gate-to-drain access region, leading a different degradation phenomena compared to the case under a low drain bias stress. Furthermore, we found that the devices are stressed under a different source current stress show a similar degradation phenomenon. This suggests that, in the cascode circuit topology, the instability degradation is still mainly triggered by the drain bias.
Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors
(2017-08-01)
Wu, Chih-Chiang
;
Jeng, Shyr-Long
;
機械工程學系
;
Department of Mechanical Engineering
This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT). Using the JFET to simulate the MIS-HEMT not only ensures that the curve fits an S-shape transfer characteristic but also enables the pinch-off voltages extracted from the threshold voltage of the MIS-HEMT to be used as a watershed to distinguish where the drop in parasitic capacitance occurs. Parameter extraction was based on static and dynamic characteristics, which involved simulating the behavior of the created GaN FET model and comparing the extracted parameters with experimental measurements to demonstrate the accuracy of the simulation program with an integrated circuit emphasis (SPICE) model. Cascode capacitance was analyzed and verified through experimental measurements and SPICE simulations. The analysis revealed that the capacitance of low-voltage MOSFETs plays a critical role in increasing the overall capacitance of cascode GaN FETs. The turn-off resistance mechanism effectively described the leakage current, and a double-pulse tester was used to evaluate the switching performance of the fabricated cascode GaN FET. LTspice simulation software was adopted to compare the experimental switching results. Overall, the simulation results were strongly in agreement with the experimental results.
High-Performance LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs With 850-V 0.98-m Omega.cm(2) for Power Device Applications
(2018-01-01)
Wang, Huan-Chung
;
Lumbantoruan, Franky Juanda
;
Hsieh, Ting-En
;
Wu, Chia-Hsun
;
Lin, Yueh-Chin
We demonstrate the electrical performances of the quaternary InAlGaN/GaN MIS-HEMTs with high quality SiNx gate dielectric and surface passivation layer deposited by low pressure chemical vapor deposition (LPCVD) at 780 degrees C. Excellent LPCVD-SiNx/InAlGaN interface and SiNx film quality were obtained, resulting in very high output current density, a very small threshold voltage hysteresis and steep subthreshold slope. The LPCVD-SiNx/InAlGaN/GaN MIS-HEMT device exhibited high on/off current ratio, large gate voltage swing, high breakdown voltage, and very low dynamic on-resistance (R-ON) degradation, meaning effective current collapse suppression compared to the plasma enhanced chemical vapor deposition -SiN x /InAlGaN/GaN MIS-HEMTs. The corresponding specific on-resistance (RoN, sp ) for LPCVD-SiN x device was as low as 0.98 m Omega.cm(2), yielding a high figure of merit of 737 MW/cm(2) . These results demonstrate a great potential of the LPCVD-SiNx /InAlGaN/GaN MIS-HEMTs for high-power switching applications.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Quang Ho Luc
;
Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
Enhancement-Mode GaN MIS-HEMTs With LaHfOx Gate Insulator for Power Application
(2017-08-01)
Lin, Yueh Chin
;
Huang, Yu Xiang
;
Huang, Gung Ning
;
Wu, Chia Hsun
;
Yao, Jing Neng
This letter reports an E-mode GaN MIS-HEMT using a composite La2O3/HfO2 gate insulator for power device applications. The composite dielectric formed an amorphous LaHfOx layer after post-deposition annealing. The GaN MIS-HEMT with amorphous LaHfOx gate dielectric showed good oxide film quality and excellent HfLaOx/GaN interface properties, as demonstrated by the measured C-V characteristics. Consequently, the E-mode MIS-HEMT was determined to show good V-th stability with only a slight increase in the dynamic R-on after high drain bias stress.
AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.

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