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Neuro-Inspired-in-Memory Computing Using Charge-Trapping MemTransistor on Germanium as Synaptic Device
(2020-09-01)
Chou, Yu-Che
;
Tsai, Chien-Wei
;
Yi, Chin-Ya
;
Chung, Wan-Hsuan
;
Wang, Shin-Yuan
In this work, we fabricated charge-trapping MemTransistors (CTMTs) on a germanium (Ge) substrate with a single-charge-trapping-layer gate-stack or a double-charge-trapping-layer gate-stack. We first constructed the energy band diagram of two gate stacks using transmission electron microscope (TEM) images and by X-ray photoelectron spectroscopy analysis. We deposited Al2O3 as a tunneling layer and a barrier layer using an atomic layer deposition (ALD) system while depositing HfO2 by ALD as the charge-trapping layer whose conduction band offset with respect to Al2O3 is 1.74 eV. Next, we demonstrated the memory characteristics of the CTMTs. By implementing the double-charge-trapping-layer gate-stack on the CTMT, we were able to enlarge the memory windows by 372 mV, improve the retention by 2.7%, and reduce the read disturbance. Furthermore, we demonstrated the synaptic device characteristics of the CTMTs. With the optimization of pulse schemes, we reduced the nonlinearity of potentiation (alpha(p)) and depression (alpha(d)) from 8.62 and -6.01 to 0.71 and 0.01, respectively, enlarged the ON/OFF ratio from 10.2 to 66.2, and increased the recognition accuracy from 24.5% to 82.1% simultaneously. With the implementation of the double-charge-trapping-layer gate-stack, we could further enlarge the ON/OFF ratio to 75.3 and increase the recognition accuracy to 86.5% simultaneously.
Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits
(2019-05-01)
Li, Yiming
;
Chen, Chieh-Yang
;
Chuang, Min-Hui
;
Chao, Pei-Jung
;
電機工程學系
In this study, we investigate direct current (DC)/alternating current (AC) characteristic variability induced by work function fluctuation (WKF) with respect to different nanosized metal grains and the variation of aspect ratios (ARs) of channel cross-sections on a 10 nm gate gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFET) device. The associated timing and power fluctuations of the GAA NW complementary metal-oxide-semiconductor (CMOS) circuits are further estimated and analyzed simultaneously. The experimentally validated device and circuit simulation running on a parallel computing system are intensively performed while considering the effects of WKF and various ARs to access the device's nominal and fluctuated characteristics. To provide the best accuracy of simulation, we herein calibrate the simulation results and experimental data by adjusting the fitting parameters of the mobility model. Transfer characteristics, dynamic timing, and power consumption of the tested circuit are calculated using a mixed device-circuit simulation technique. The timing fluctuation mainly follows the trend of the variation of threshold voltage. The fluctuation terms of power consumption comprising static, short-circuit, and dynamic powers are governed by the trend that the larger the grain size, the larger the fluctuation.
Thickness Effect on Operational Modes of ZnGa2O4 MOSFETs
(2018-01-01)
Cheng, Li-Chung
;
Huang, Chiung-Yi
;
Horng, Ray-Hua
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The device mechanism from depletion to enhancement mode for ZnGa2O4 metal-oxide semiconductor field effect transistors (MOSFETs) grown on the sapphire substrate by metalorganic chemical-vapor deposition was studied. It was found that the thickness of the ZnGa2O4 thin-film would affect the operational mode of the MOSFETs. Under the low-voltage operation (V-DS = 0.5 V), the transistors exhibited a high on/off ratio from 10(7) to 10(4), low subthreshold swing from 150 to 330 mV/dec, high field-effect mobility from 4.2 to 0.054 cm(2)/V-s and threshold voltages from - 17.8 to 4.1 V (using constant current = 1 nA). These electrical properties all depend on the thickness of the ZnGa2O4 thin-film transistors. Finally, the e-mode ZnGa2O4 thin-film transistor with off-state breakdown voltage over 400 V is fabricated.
On Statistical Variation of MOSFETs Induced by Random-Discrete-Dopants and Random-Interface-Traps
(2012)
Li, Yiming
;
Su, Hsin-Wen
;
Chen, Chieh-Yang
;
Cheng, Hui-Wen
;
Chen, Yu-Yu
In this work, we statistically study characteristic fluctuation of 16-nm-gate high-kappa/metal gate (HKMG) MOSFETs by random-discrete-dopants (RDDs) inside silicon channel and random-interface-traps (RITs) at high-kappa/silicon interface. Randomly generated devices with three-dimensional (3D) RDDs inside device channel and 2D RITs at HfO2/Si interface are incorporated into quantum mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to RITs near the source and drain ends, and RDDs near the device channel surface and silicon substrate. Characteristic fluctuations are affected to different extents by the random combinatorial RDDs and RITs. Nonlinearly correlated RDDs and RITs further violate the statistical assumption of independent identical distributions between the RDDs- and RITs-induced random variables. Consequently, for the studied 16-nm-gate HKMG MOSFETs, the threshold voltage fluctuation induced by the combined RDs and ITs is less than their statistical sum due to local interaction of surface potentials resulting from the RDDs and RITs simultaneously. In contrast to RDDs fluctuation, the screening effect of device\'s inversion layer cannot effectively screen potential\'s variation resulting from RITs; thus, devices still have noticeable gate capacitance characteristic fluctuation under high gate bias.
非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究
(2008)
陳明哲
;
CHEN MING-JER
;
國立交通大學電子工程學系及電子研究所
本計劃為期三年，進行非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究。第一年以我們的 2005 年Physical Review-B 奈米尺寸陷阱物理論文為基礎，實驗決定0.15 um 製程快閃式記憶體tunnel 氧化層中中奈米尺寸陷阱的能量系統圖，此快閃式記憶體由學術界合作對像以及記憶體知名大廠等提供。同時進行電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗 (作法可參考我們的2005 年IEEE TED 快閃式記憶體論文) ，以進行可靠性物理研究。此可靠性物理即是整合我們的歷年來於氧化層陷阱物理機制以及快閃式記憶體相關議題發表的論文並予以應用，自然也包括我們的Physical Review-B 奈米尺寸陷阱物理論文之應用。也要積極針對我們的奈米尺寸陷阱物理論文所建立的基礎，理論上作一個更為深入的研究建立一牽涉波函數的量子力學數值模式，得以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理。第二年繼續電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。此第二年的快閃式記憶體元件應為 0.13 um 製程者。繼續從學術界合作對像取得更多快閃式記憶體測試元件。也進行Hall 效應量測，提供較深入的實驗數據。延續氧化層奈米尺寸陷阱物理研究，進一步應用於快閃記憶體，即針對氧化層中量子點或量子晶體，利用波函數及能量系統分佈的角度來處理，相互比較並將之關聯。第三年繼續電性量測0.11 um 或 90 nm 製程快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。前兩年理論應用結果送至學術界合作對像以及國際知名大廠等參考以為實際研發較具實用的次世代快閃記憶體。也繼續Hall 效應量測以及次臨界級雜訊量測，再度深一層驗證理論。最後一年裡，積極應用嚴謹的牽涉波函數的量子力學數值模式 (可以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理): 藉由自我量測數據及論文數據比較，對於不同尺寸元件結構進行比較分析，並對下世代元件走向及應用潛力作一預估，且要探討量子點在氧化層中位置分佈對於整體系統的特性影響，更考慮在高溫操作下，資料保存的正確無誤，以此作為設計電路的基礎經驗，並嘗試提出設計的最佳化以供次世代快閃記憶體電路設計之用。
非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究
(2006)
陳明哲
;
CHEN MING-JER
;
交通大學電子工程系
本計劃為期三年，進行非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究。第一年以我們的2005 年Physical Review-B 奈米尺寸陷阱物理論文為基礎，實驗決定0.15 um 製程快閃式記憶體tunnel 氧化層中中奈米尺寸陷阱的能量系統圖，此快閃式記憶體由學術界合作對像以及記憶體知名大廠等提供。同時進行電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗 (作法可參考我們的2005 年IEEE TED 快閃式記憶體論文) ，以進行可靠性物理研究。此可靠性物理即是整合我們的歷年來於氧化層陷阱物理機制以及快閃式記憶體相關議題發表的論文並予以應用，自然也包括我們的Physical Review-B 奈米尺寸陷阱物理論文之應用。也要積極針對我們的奈米尺寸陷阱物理論文所建立的基礎，理論上作一個更為深入的研究建立一牽涉波函數的量子力學數值模式，得以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理。第二年繼續電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。此第二年的快閃式記憶體元件應為 0.13 um 製程者。繼續從學術界合作對像取得更多快閃式記憶體測試元件。也進行Hall 效應量測，提供較深入的實驗數據。延續氧化層奈米尺寸陷阱物理研究，進一步應用於快閃記憶體，即針對氧化層中量子點或量子晶體，利用波函數及能量系統分佈的角度來處理，相互比較並將之關聯。第三年繼續電性量測0.11 um 或 90 nm 製程快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。前兩年理論應用結果送至學術界合作對像以及國際知名大廠等參考以為實際研發較具實用的次世代快閃記憶體。也繼續Hall 效應量測以及次臨界級雜訊量測，再度深一層驗證理論。最後一年裡，積極應用嚴謹的牽涉波函數的量子力學數值模式 (可以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理): 藉由自我量測數據及論文數據比較，對於不同尺寸元件結構進行比較分析，並對下世代元件走向及應用潛力作一預估，且要探討量子點在氧化層中位置分佈對於整體系統的特性影響，更考慮在高溫操作下，資料保存的正確無誤，以此作為設計電路的基礎經驗，並嘗試提出設計的最佳化以供次世代快閃記憶體電路設計之用。
非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究
(2007)
陳明哲
;
CHEN MING-JER
;
國立交通大學電子工程學系及電子研究所
本計劃為期三年，進行非揮發性記憶體奈米尺寸陷阱物理暨相關可靠性物理之嶄新研究。第一年以我們的2005 年Physical Review-B 奈米尺寸陷阱物理論文為基礎，實驗決定0.15 um 製程快閃式記憶體tunnel 氧化層中中奈米尺寸陷阱的能量系統圖，此快閃式記憶體由學術界合作對像以及記憶體知名大廠等提供。同時進行電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗 (作法可參考我們的2005 年IEEE TED 快閃式記憶體論文) ，以進行可靠性物理研究。此可靠性物理即是整合我們的歷年來於氧化層陷阱物理機制以及快閃式記憶體相關議題發表的論文並予以應用，自然也包括我們的Physical Review-B 奈米尺寸陷阱物理論文之應用。也要積極針對我們的奈米尺寸陷阱物理論文所建立的基礎，理論上作一個更為深入的研究建立一牽涉波函數的量子力學數值模式，得以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理。第二年繼續電性量測快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。此第二年的快閃式記憶體元件應為 0.13 um 製程者。繼續從學術界合作對像取得更多快閃式記憶體測試元件。也進行Hall 效應量測，提供較深入的實驗數據。延續氧化層奈米尺寸陷阱物理研究，進一步應用於快閃記憶體，即針對氧化層中量子點或量子晶體，利用波函數及能量系統分佈的角度來處理，相互比較並將之關聯。第三年繼續電性量測0.11 um 或 90 nm 製程快閃式記憶體元件的特性以及長時間加速劣化實驗，進行可靠性物理深入研究。前兩年理論應用結果送至學術界合作對像以及國際知名大廠等參考以為實際研發較具實用的次世代快閃記憶體。也繼續Hall 效應量測以及次臨界級雜訊量測，再度深一層驗證理論。最後一年裡，積極應用嚴謹的牽涉波函數的量子力學數值模式 (可以在同一能量系統下整合奈米尺寸陷阱和氧化層中量子點或量子晶體物理): 藉由自我量測數據及論文數據比較，對於不同尺寸元件結構進行比較分析，並對下世代元件走向及應用潛力作一預估，且要探討量子點在氧化層中位置分佈對於整體系統的特性影響，更考慮在高溫操作下，資料保存的正確無誤，以此作為設計電路的基礎經驗，並嘗試提出設計的最佳化以供次世代快閃記憶體電路設計之用。
The combined effects of nitrogen implantation at S/D extension and N2O oxide on 0.18 mu m N- and P-metal oxide field effect transistors (MOSFETs)
(1999-12-01)
Chao, TS
;
Chang, SJ
;
Chien, CH
;
Lin, HC
;
Huang, TY
The combined effects of N-2-implantation at S/D extension and N2O oxide on 0.18 mu m n- and p-Metal oxide field effect transistors (MOSFETs) were investigated. It is found that for n-channel transistors, V-th roll-off and drain-induced barrier lowering (DIBL) are enhanced by nitrogen incorporation through either N2O oxide or N-2-implantatian. However, for p-channel transistors, apposite trends are observed for N2O oxide and N-2-implantation. Finally, nitrogen incorporation by either method is found to improve the interface quality for nMOSFETs. While for p-channel transistors, best results are obtained by the combined effects of N2O oxide and N-2-implantation.
Edge hole direct Tunneling leakage in ultrathin gate oxide p-channel MOSFETs
(2001-12-01)
Yang, KN
;
Huang, HT
;
Chen, MJ
;
Lin, YM
;
Yu, MC
This paper examines the edge direct tunneling (EDT) of holes from p(+) polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T-OX = 1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E-OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E-OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E-OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected.
A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells
(2002-07-01)
Cho, CYS
;
Chen, MJ
;
Lin, JH
;
Chen, CF
;
電子工程學系及電子研究所
Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I-D = I-o exp[q(V-GB - nV(SB))/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients.

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