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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 10 of 19
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    A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
    (2019-12-01)
    Wang, Shih-Hsing
    ;
    Hung, Chung-Chih
    ;
    電機資訊學士班
    ;
    Undergraduate Honors Program of Electrical Engineering and Computer Science
    For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-W power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of -105.7 dBc/Hz at 1-MHz frequency offset with 20 s locking time.
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    A CMOS Phase to Digital Converter for Optical Encoders
    (2011-01-01)
    Chiang, Cheng-Ta
    ;
    Hsieh, Kaun-Chun
    ;
    Huang, Yu-Chung
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    In this paper, a CMOS phase to digital converter for optical encoders is newly proposed. This chip adopts a proposed phase-shift method to easily generate phase shifts of signals by using a resistor chain. Different to PLL-based and ADC-based interpolation, the complexity and hardware cost can be relaxed in this proposed chip. Based upon the device parameters of 0.5 mu m 2P2M CMOS technology with 5 V power supply, all the functions and performance of the proposed CMOS phase to digital converter for optical encoders are successfully tested and proven through SPICE simulations. The physical layout of interpolation circuits and current to voltage converter are 1000 x 600 mu m(2) and 850 x 760 mu m(2), respectively. The proposed chip is suitable for optical encoders.
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    A CMOS Phase to Digital Transducer for Optical Incremental Sensors
    (2011-01-01)
    Chiang, Cheng-Ta
    ;
    Hsieh, Kaun-Chun
    ;
    Huang, Yu-Chung
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    In this paper, a CMOS phase to digital transducer for optical incremental sensors is newly proposed. This chip adopts a proposed phase-shift method to easily generate phase shifts of signals by using a resistor chain. Different to PLL-based and ADC-based interpolation, the complexity and hardware cost can be relaxed in this proposed chip. Based upon the device parameters of 0.5 mu m 2P2M CMOS technology with 5 V power supply, all the functions and performance of the proposed CMOS phase to digital transducer for optical incremental sensors are successfully tested and proven through measurements. The physical layout including ESD I/O pads is 2010 x 1500 mu m(2). The proposed chip is suitable for optical incremental sensors.
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    A 34-42GHz Single-Side-Band Transmitter with Switchable VCO/PLL in 90nm-CMOS Process
    (2017-01-01)
    Huang, Ching-Ying
    ;
    Wu, Kun-Long
    ;
    Hu, Robert
    ;
    Chang, Chi-Yang
    ;
    電子工程學系及電子研究所
    This manuscript describes a 34-42GHz single-sideband 90nm-CMOS transmitter where PLL has been integrated into the LO chain and, with I/Q input and two-stage up-conversion, a 30dB image-rejection ratio is achieved within the intended bandwidth. This transmitter's wideband tuning range is made possible by the use of additional capacitor on the VCO, and the phase noise of the resulting RF output is in the range of -70 to -90dBc/Hz at 1MHz, and all below 100dBc/Hz at 10MHz. The circuit's IF-to-RF conversion gain is 30dB, with saturated output power around 5dBm, and the total power consumption is 260mW. Through the control of the power amplifier's drain bias, a 50dB power level difference can be obtained, thus allows signal modulation and further combination with the receiver. This 1100x650um(2) transmitter can be used as a prototypical circuit to explore next-generation mobile communication and civilian radar array systems.
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    A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
    (2014)
    Hong, Zheng-Hao
    ;
    Chen, Wei-Zen
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm(2) only.
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    A Delta Sigma TDC with Sub-ps Resolution for PLL Built-in Phase Noise Measurement
    (2016)
    Chen, Wei-Zen
    ;
    Kuo, Po-I
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A sub-ps Delta Sigma TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and Delta Sigma TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm(2).
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    次微米通信用高頻標準元晶片設計及測試(III)
    (1998)
    吳介宗
    ;
    交通大學電子工程系
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    A 1.5-V 3 similar to 10-GHz 0.18-mu m CMOS Frequency Synthesizer for MB-OFDM UWB Applications
    (2008)
    Huang, Zue-Der
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    Kuo, Fong-Wei
    ;
    Wang, Wen-Chieh
    ;
    Wu, Chung-Yu
    ;
    電子工程學系及電子研究所
    An Ultra wide band (UWB) frequency synthesizer is designed and fabricated in 0.18-mu m CMOS technology to generate all the carrier frequencies for 13 bands distributed from 3 to 10 GHz. It is composed of one phase-locked loop (PLL) and three single-side band (SSB) mixers. The polyphase filter is used to generate all needed quadrature signals in the circuit and band selectors are to select the frequency band. The sideband rejection can be over 30dB. The switching time between bands is around 3.75ns. The current consumption is 72mA under 1.5-V power supply.
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    Applicability of phase-locked loop to tracking the rhythmic activity in EEGS
    (2000)
    Lo, PC
    ;
    Lee, YY
    ;
    電控工程研究所
    ;
    Institute of Electrical and Control Engineering
    Conventional methods of spectral analysis are based on mathematical or numerical algorithms applied to digitized signals. This paper discusses the applicability of the phase-locked loop (PLL) approach for tracking electroencephalogram (EEG) rhythmic bands (delta, theta, alpha, or beta). The use of the PLL for frequency tracking should also aid the development of online EEG interpretation and screening based on frequency characteristics when the PLL is realized by hardware. As a result, two factors in the applicability of the PLL are: (1) translation of the EEG spectrum to a higher-frequency band by a single-sideband (SSB) modulation scheme, and (2) the narrowband spectral feature of the EEG-a small difference between two major frequencies. The PLL output is further quantized according to the EEG rhythmic bands. Our analysis shows that the integrated system is capable of tracking the EEG rhythmic patterns.
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    A Spur-Reduction Frequency Synthesizer For WIMAX Applications
    (2010)
    Liao, De-Wen
    ;
    Hung, Chung-Chih
    ;
    電機工程學系
    ;
    Department of Electrical and Computer Engineering
    A spur-reduction frequency synthesizer proposed in 0.18-um CMOS technology is developed for WIMAX applications. It incorporates a random charge pump to randomize the reference spur so as to accomplish a low spur level or a relatively smooth spectrum and a fast lock synthesizer. This frequency synthesizer achieves the phase noise of -124dBc/Hz at 1MHz offset frequency and reference spurs below -70dBc. The spur tones of the frequency synthesizer are greatly in frequency domain and the power consumption is 28mW.