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🏛️國立陽明交通大學機構典藏

Subject: search.filters.subject.RF

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Now showing 1 - 10 of 24
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    A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications
    (2018-01-01)
    Li, Yilei
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    Dhwaj, Kirti
    ;
    Wong, Chien-Heng
    ;
    Du, Yuan
    ;
    Du, Li
    In this paper, a fully synthesizable all-digital transmitter (ADTX) is first proposed. This transmitter (TX) uses Cartesian architecture and supports wide-band quadratic-amplitude modulation with wide carrier frequency range. Furthermore, the design methodology for ADTX and corresponding bandpass filter is discussed. This TX is synthesized with digital register transfer level-graphic database system flow, and can be easily implemented in any standard CMOS technology. An exemplary TX is synthesized by TSMC 28-nm standard cell library with extremely small area (0.0009 mm(2)) and supports carrier frequency as high as 6 GHz with excellent error vector magnitude (<-30 dB). To the best of the authors' knowledge, this is the first work on a fully synthesizable design of RF transistors, allowing easy technology migration and portability.
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    RF WIRELESS LC TANK SENSORS FABRICATED BY 3D ADDITIVE MANUFACTURING
    (2015)
    Wu, Sung-Yueh
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    Yang, Chen
    ;
    Hsu, Wensyang
    ;
    Lin, Liwei
    ;
    交大名義發表
    We present wireless inductor-capacitor (LC) tank sensors constructed by the three-dimensional (3D) additive manufacturing technique. Fabricated 3D structures with hollow channels are filled with liquid metal (silver particles) to form basic electrical components including inductors and capacitors. In the prototype design, a radio-frequency (RF) LC tank with resonance frequency at 0.53 GHz is realized. This LC tank sensor is utilized in rapid detection of liquid food (e.g., milk and juice). Specifically, the resonant frequency of the LC tank changes as the dielectric constant of the liquid food deteriorates over time and the signals are detected via an inductively coupled reader wirelessly. In the preliminary tests, a 4.3% frequency shift for milk stored at room temperature after 36 hours was obtained. This work presents a new class of manufacturing concepts to construct arbitrary 3D electrical systems for wireless sensing applications.
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    Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
    (2014-11-01)
    Lin, Chun-Yu
    ;
    Fan, Mei-Lian
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
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    奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫三：奈米CMOS技術之60∼110-GHz射頻前端關鍵性積體電路之研究與設計
    (2008)
    胡樹一
    ;
    Hu Shu-I
    ;
    國立交通大學電子工程學系及電子研究所
    應用於傳遞高品質視訊影像的家用無線網路在不久的將來將變的普及，高速以及高 資料量的傳送，將使區域性的寬頻無線通訊系統的需求更為提高。因此，如何設計應用 於更高操作頻段的無線傳輸系統，如60~110-GHz 之V-Band 與W-Band 之區域性無線通 訊系統，將是一個重要的研究主題。 隨著CMOS 製程由深次微米(deep submicron)進步到奈米(nanometer)，電晶體的最高 操作頻率(ft)已超過100GHz，使用奈米CMOS 製程，設計操作頻率在60~110-GHz 之 V-Band 與W-Band 的射頻積體電路已經可望實現。 本計畫將以130nm ~ 45nm之奈米CMOS技術來研究並設計操作頻率在60~110-GHz 的高頻段無線通訊收發器之前端主要電路元件。首先將以130-nm 與90-nm CMOS 製程 技術，設計操作頻率於60 GHz 的V-Band 射頻前端接收器與發射器電路；延續設計 60-GHz 頻段之前端電路的知識，設計應用於W-Band 頻帶之窄頻與寬頻之射頻前端接 收器與發射器之主要關鍵電路。此外，本計畫也將針對所設計的V-Band 與W-Band 射 頻關鍵性電路進行低功率以及高性能的改善，使電路在高頻操作下具有高性能外，亦能 具有低電壓低功率消耗的特性。此外，亦將進行前瞻性研究，以創新的觀念設計電路， 期望能將各主要的前端電路元件之性能推至極限。 預計完成的主要前端電路元件有：低雜訊放大器、混波器、震盪器、除頻器以及功 率放大器；各元件的功能及設計考量簡述如下: 1. 低雜訊放大器 (Low-Noise Amplifier)： 低雜訊放大器的目的在於提供足夠的增益以及低的雜訊指數(NF)，以降低後級 電路對雜訊的影響，對整個系統的靈敏度有決定性的影響。此計畫除了針對雜訊指 數的特性改善外，也將設計使其有較低的功率消耗。 2. 混波器 (Mixer)： 混波器目的在將射頻訊號與本地震盪訊號相乘，使訊號頻率降至中頻或基頻； 或將中頻或基頻訊號與本地振盪訊號相乘，使訊號升至為射頻訊號。設計上為了使 系統的動態範圍提高，混波器需有足夠的線性度(linearity)，以提高動態區間(dynamic range)。 3. 震盪器(VCO)： 震盪器目的是產生本地震盪訊號，提供混波器將訊號進行升降頻使用。設計上，震盪器需要有好的相位雜訊(phase noise)，高頻率調整範圍，以及低功率的特 性。 4. 除頻器(Frequency Divider) 高頻除頻器為頻率合成器中的一個重要元件，此電路將震盪器的輸出頻率先行 除頻，以使後端的電路處理較為低頻率的訊號，進而降低整體的功率消耗。此高頻 除頻器在設計上，要能處理寬頻的輸入訊號，同時低功率消耗也是重要的考量。 5. 功率放大器 (Power Amplifier)： 功率放大器的目的在將射頻訊號放大並驅動天線將訊號發射出去，為使訊號在 傳遞時減少失真，以及降低功率消耗，功率放大器需有優良的功率效益以及好的線 性度。 在實現及量測驗證過此計畫中之各元件的功能後，將進一步與其他子計畫成果整 合，以應用於無線通訊之收發器系統，並同時改善各電路元件的特性。預計此三年期間 完成多個主要關鍵性的電路方塊，以運用於未來的57~64-GHz 頻段以及75~110-GHz 之 無線通訊傳送接收機與傳送機之使用；同時，本三年型研究計畫也將整合已開發的 60-GHz 頻段之關鍵性主要電路，並實現57~64-GHz 之V-Band 寬頻無線通訊系統，並 將此系統實際地應用在高速高資料量的訊息傳輸上。
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    RF CMOS之特性量測、模式建立與可靠性研究
    (2000)
    汪大暉
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    WANG TAHUI
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    交通大學電子工程系
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    Temperature-Dependent RF Small-Signal and Noise Characteristics of SOI Dynamic Threshold Voltage MOSFETs
    (2010-09-01)
    Wang, Sheng-Chun
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    Su, Pin
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    Chen, Kun-Ming
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    Liao, Kuo-Hsiang
    ;
    Chen, Bo-Yuan
    In this paper, temperature-dependent RF small-signal and noise characteristics of silicon-on-insulator (SOI) dynamic threshold voltage (DT) MOSFETs are experimentally examined. In the low-voltage regime, both the cutoff and maximum oscillation frequencies (f(t) and f(max)) tend to increase with temperature. In addition, the inherent body-related parasitics and the series resistance have much more impact on f(max) than f(t). Besides, we found that the noise stemmed from the body resistance (R(b)) would contribute to the output noise current, and degrade the minimum noise figure (NF(min)). Our study may provide insights for RF circuit design using advanced SOI DT MOSFETs.
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    High-density MIM capacitors using Al2O3 and AlTiOx dielectrics
    (2002-04-01)
    Chen, SB
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    Lai, CH
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    Chin, A
    ;
    Hsieh, JC
    ;
    Liu, J
    We have investigated the electrical characteristics of Al2O3 and AlTiOx MIM capacitors from IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 muF/cm(2) are obtained for Al2O3 and AlTiOx MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiOx MIM capacitor has very large capacitance reduction as increasing frequencies. In contrast, good device integrity has been obtained for Al2O3 MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent.
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    Frequency-dependent capacitance reduction in high-k AlTiOx and Al2O3 gate dielectrics from IF to RF frequency range
    (2002-04-01)
    Chen, SB
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    Lai, CH
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    Chan, KT
    ;
    Chin, A
    ;
    Hsieh, JC
    We have characterized the capacitance and loss tangent for high-k Al2O3 and AlTiOx gate dielectrics from IF (100 KHz) to RF (20 GHz) frequency range. Nearly the same rate of capacitance reduction as SiO2 was demonstrated individually by the proposed Al2O3 and AlTiOx gate dielectrics as frequency was increased. Moreover, both dielectrics preserve the higher k better than SiO2 from 100 KHz to 20 GHz. These results suggest that both Al2O3 and AlTiOx are suitable for next generation MOSFET application into RF frequency regime.
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    RF noise in 0.18-mu m and 0.13-mu m MOSFETs
    (2002-12-01)
    Huang, CH
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    Lai, CH
    ;
    Hsieh, JC
    ;
    Liu, J
    ;
    Chin, A
    We have studied the gate finger number and gate ength dependence on minimum noise figure (NFmin) in deep submicrometer MOSFETs. A lowest NFmin. of 0.93 dB is measured in 0.18-mum MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 mum shows larger NFmin than the 0.18-mum case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-mum MOSFET gives higher NFmin due to the higher gate resistance and a modified T-gate structure proposed to optimize the NFmin for further scaling down of the MOSFET.