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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    16奈米矽多重閘極電晶體中隨機摻雜導致之特性擾動及其抑制方法
    (2008)
    李義明
    ;
    LI YIMING
    ;
    國立交通大學電信工程學系(所)
    隨著矽製程技術的演進，超大型積體電路元件已進入次45 奈米生產技術，除了傳統製程變異效應，隨機摻雜問題所造成的擾動已嚴重的影響了場效應電晶體的特性與可靠度。在去年的計畫中 (隨機摻雜在次20 奈米矽場效應電晶體特性擾動之研究)，吾人已成功地以實驗與理論分析次20 奈米矽場效應電晶體特性之擾動，研究指出20 奈米電晶體臨界電壓的隨機摻雜擾動將高達40 mV，此模擬結果與台積電的實際量測結果(39 mV)非常吻合，此結果已陸續發表於2007年VLSI會議以及IEEE相關期刊。 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點，新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案；其中，20 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢，因此研究隨機摻雜問題在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。延續先前計畫所開發之模擬分析方法，本計劃將以兩年之時間完整研究隨機摻雜在16奈米等級多閘極立體場效應電晶體導致的擾動問題及其抑制方法；第一年計畫將結合實驗與理論研究含平面SOI電晶體、雙閘極電晶體、三閘極SOI電晶體、三閘極塊材電晶體、方塊全閘極電晶體、圓形全閘極電晶體、類圓形全閘極電晶體，…等立體元件隨機摻雜導致的電特性擾動，其中關於閘極長度暨製程線寬變化導致的擾動也將一起分析。同時為了壓抑次20 奈米元件中高達40 mV 以上的臨界電壓擾動，吾人於第二年計畫將針對上述的平面與多閘極立體電晶體，在兼具高性能電特性要求之前提下，找尋壓抑擾動之物理機制並從材料與製程之觀點提出有效壓抑擾動的方法，如：摻雜分布之最佳化、閘極工程與閘極高介電材料的使用，…等等，並與台積電進行實驗驗證與製程最佳化。最後根據所研究之壓抑擾動的物理機制與實驗數據，推演能準確描述隨機摻雜導致電特性擾動的解析公式。
  • Thumbnail Image
    Item type:Item,
    16奈米矽多重閘極電晶體中隨機摻雜導致之特性擾動及其抑制方法
    (2009)
    李義明
    ;
    LI YIMING
    ;
    國立交通大學電信工程學系(所)
    隨著矽製程技術的演進，超大型積體電路元件已進入次45 奈米生產技術，除了傳統製程變異效應，隨機摻雜問題所造成的擾動已嚴重的影響了場效應電晶體的特性與可靠度。在去年的計畫中 (隨機摻雜在次20 奈米矽場效應電晶體特性擾動之研究)，吾人已成功地以實驗與理論分析次20 奈米矽場效應電晶體特性之擾動，研究指出20 奈米電晶體臨界電壓的隨機摻雜擾動將高達40 mV，此模擬結果與台積電的實際量測結果(39 mV)非常吻合，此結果已陸續發表於2007年VLSI會議以及IEEE相關期刊。 延續摩爾定律而獲得高性能矽晶片以及高密度元件之觀點，新材料、新製程與新結構的開發是半導體製造上繼續微縮元件的尺寸最有效的策略方案；其中，20 奈米之後電晶體結構的改變儼然已成為非常前瞻與重要的趨勢，因此研究隨機摻雜問題在多重閘極場效電晶體特性之影響已為重要且急迫之課題之一。延續先前計畫所開發之模擬分析方法，本計劃將以兩年之時間完整研究隨機摻雜在16奈米等級多閘極立體場效應電晶體導致的擾動問題及其抑制方法；第一年計畫將結合實驗與理論研究含平面SOI電晶體、雙閘極電晶體、三閘極SOI電晶體、三閘極塊材電晶體、方塊全閘極電晶體、圓形全閘極電晶體、類圓形全閘極電晶體，…等立體元件隨機摻雜導致的電特性擾動，其中關於閘極長度暨製程線寬變化導致的擾動也將一起分析。同時為了壓抑次20 奈米元件中高達40 mV 以上的臨界電壓擾動，吾人於第二年計畫將針對上述的平面與多閘極立體電晶體，在兼具高性能電特性要求之前提下，找尋壓抑擾動之物理機制並從材料與製程之觀點提出有效壓抑擾動的方法，如：摻雜分布之最佳化、閘極工程與閘極高介電材料的使用，…等等，並與台積電進行實驗驗證與製程最佳化。最後根據所研究之壓抑擾動的物理機制與實驗數據，推演能準確描述隨機摻雜導致電特性擾動的解析公式。
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    Interface traps and random dopants induced characteristic fluctuations in emerging MOSFETs
    (2011-07-01)
    Li, Yiming
    ;
    Cheng, Hui-Wen
    ;
    Chiu, Yung-Yueh
    ;
    傳播研究所
    ;
    電機工程學系
    In this work, we study the effect of interface traps (ITs) and random dopants (RDs) on characteristics of 16-nm MOSFETs. Totally random generated devices with 2D ITs between the interface of silicon and HfO(2) film as well as 3D RDs inside the silicon channel are simulated. Fluctuations of threshold voltage and on/ off state current for devices with different EOT of insulator film are analyzed and discussed. The results of this study indicate ITs and RDs statistically correlate to each other and RDs govern device variability, compared with the influence of ITs. Notably, the position of ITs and RDs induces rather different fluctuation in spite of the same number of ITs and RDs are investigated. (C) 2011 Elsevier B.V. All rights reserved.
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    Quantum hydrodynamic simulation of discrete-dopant fluctuated physical quantities in nanoscale FinFET
    (2011-01-01)
    Li, Yiming
    ;
    Cheng, Hui-Wen
    ;
    Han, Ming-Hung
    ;
    傳播研究所
    ;
    電機工程學系
    Impact of the discrete dopants on device performance is crucial in determining the behavior of nanoscale semiconductor devices Atomistic quantum mechanical device simulation for studying the effect of discrete dopants on device s physical quantities is urgent This work explores the physics of discrete-dopant-induced characteristic fluctuations in 16-nm fin-typed field effect transistor (FinFET) devices Discrete dopants are statistically positioned in the three-dimensional channel region to examine associated carrier's characteristic concurrently capturing "dopant concentration variation" and "dopant position fluctuation" An experimentally validated quantum hydrodynamic device simulation was conducted to investigate the potential profile and threshold voltage fluctuations of the 16-nm FinFET Results of this study provide further insight into the problem of fluctuation and the mechanism of immunity against fluctuation in 16-nm devices (C) 2010 Elsevier BV All rights reserved
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    A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation
    (2006-07-01)
    Li, Yiming
    ;
    Yu, Shao-Ming
    ;
    資訊工程學系
    ;
    電信工程研究所
    ;
    Department of Computer Science
    In this paper, we computationally investigate fluctuations of the threshold voltage introduced by random dopants in nanoscale double gate metal-oxide-semiconductor field effect transistors (DG MOSFETs). To calculate variance of the threshold voltage of nanoscale DG MOSFETs, a quantum correction model is numerically solved with the perturbation and the monotone iterative techniques. Fluctuations of the threshold voltage resulting from the random dopant, the gate oxide thickness, the channel film thickness, the gate channel length, and the device width are calculated. Quantum mechanical and classical results have similar prediction on fluctuations of the threshold voltage with respect to different designing parameters including dimension of device geometry as well as the channel doping. Fluctuation increases when the channel doping, the channel film thickness, and/or the gate oxide thickness increase. On the other hand, it decreases when the channel length and/or the device width increase. Calculations of the quantum correction model are quantitatively higher than that of the classical estimation according to different quantum confinement effects in nanoscale DG MOSFETs. Due to good channel controllability, DG MOSFETs possess relatively lower fluctuation, compared with the fluctuation of single gate MOSFETs (less than a half of the fluctuation[-11pc] of SG MOSFETs). To reduce fluctuations of the threshold voltage, epitaxial layers on both sides of channel with different epitaxial doping are introduced. For a certain thickness of epitaxial layers, the fluctuation of the threshold voltage decreases when epitaxial doping decreases. In contrast to conventional quantum Monte Carlo approach and small signal analysis of the Schrodinger-Poisson equations, this computationally efficient approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
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    Process-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devices
    (2009-03-01)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Cheng, Hui-Wen
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    Impact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V(th) fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property, Result of this study confirms the suppression of V(th) fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application. (C) 2008 Elsevier B.V. All rights reserved.
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    Reduction of Discrete-Dopant-Induced High-Frequency Characteristic Fluctuations in Nanoscale CMOS Circuit
    (2008)
    Li, Yiming
    ;
    Hwang, Chih-Hong
    ;
    Yeh, Ta-Ching
    ;
    Huang, Hsuan-Ming
    ;
    Li, Tien-Yeh
    As the dimension of semiconductor device shrunk into nanoscale, characteristic fluctuation is more pronounced, and become crucial for circuit design. Diverse approaches have been reported to investigate and suppress the random-dopant-induced fluctuations in devices. However, attention is seldom drawn to the existence of high-frequency characteristic fluctuations of active device. In this paper, intrinsic high-frequency characteristic fluctuations of the nanoscale MOSFET circuit induced by random dopants are intensively explored using an experimentally validated simulation methodology, where fluctuation suppression technique is further examined. The circuit gain, the 3db bandwidth and the unity-gain bandwidth of the tested circuit are estimated concurrently capturing the discrete-dopant-number-and discrete-dopant-position-induced fluctuations. This study provides an insight into discrete-dopant-induced intrinsic high-frequency characteristic fluctuations and examines the potential fluctuation suppression technique for nanoscale transistor circuit.