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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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    Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
    (2011-04-01)
    Chou, Y. L.
    ;
    Chung, Y. T.
    ;
    Wang, Tahui
    ;
    Ku, S. H.
    ;
    Zou, N. K.
    Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.
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    A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices
    (2017-03)
    Guo, Jyh-Chyurn
    ;
    Du, Pei-Ying
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps (Delta N-it), localized charges (Delta N-ot), and trapped holes (Delta N-hole) in P-SONOS cell devices. Charge pumping current (I-CP) measurement can be used to probe Delta N-it and Delta N-ot from the increase of maximum I-CP (I-CP,I- max) and the shift of I-CP curve along the base level voltage (V-b). When increasing the program and erase (P/E) cycles, the negative threshold voltage (V-T) shift at both program and erase states suggests the generation of Delta N-hole. The evolution of Delta N-it, Delta N-ot, and Delta N-hole during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current (I-GIDL) and substrate current (I-SUB) as well as dramatic differences between the source and drain. The lateral migration of Delta N-ot caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger V-T shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.
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    Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
    (2017-01)
    Liu, Yu-Heng
    ;
    Jiang, Cheng-Min
    ;
    Chen, Wei-Chun
    ;
    Wang, Tahui
    ;
    Tsai, Wen-Jer
    We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
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    Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash Memory
    (2017-01)
    Liu, Yu-Heng
    ;
    Jiang, Cheng-Min
    ;
    Chen, Wei-Chun
    ;
    Wang, Tahui
    ;
    Tsai, Wen-Jer
    We investigated electric field-induced trapped electron lateralmigration in a SONOS flash cell. The threshold voltage shift (Delta V-t) andgate-induceddrain leakage(GIDL) current were measured to monitor nitride electron movement in retention. We applied different voltages to the gate and the source/drain in retention to vary the vertical and lateral electric fields. Our study shows that: 1) GIDL current can be used tomonitor trapped charge lateralmigration and 2) nitride charge lateral migration exhibits strong dependence on the lateral electric field. Based on measured temperature and field dependence, a nitride trapped charge emission process via thermally assisted tunneling is proposed for electron lateral migration. The emission rates of thermally assisted tunneling, direct trap-to-band tunneling and Frenkel-Poole emission were compared.
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    STUDY OF GATE-INJECTION OPERATED SONOS-TYPE DEVICES USING THE GATE-SENSING AND CHANNEL-SENSING (GSCS) METHOD
    (2009)
    Du, Pei-Ying
    ;
    Lue, Hang-Ting
    ;
    Wang, Szu-Yu
    ;
    Huang, Tiao-Yuan
    ;
    Hsieh, Kuang-Yeu
    SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by PIE operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we can track the charge centroid for gate-injection "top BE-SONOS" and various SONOS-type devices. Our results indicate that the charge centroid after electron gate injection is close to the nitride center, irrespective of various nitride thickness and top dielectric. Moreover, there is electron and hole vertical mismatch after hole gate injection. Comparing the results from SONS, we can clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For SNOS and SNS, where there is electron and hole injection simultaneously, two-region approximation can give us more detailed information about electron and hole capture. By comparing experimental data with theoretical modeling, we have shown that nitride 7nm or thicker captures all the injected electrons up to total charge area density similar to 10(13)cm(-2).
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    單電荷與輻射效應在先進CMOS 和SONOS 元件可靠性之統計量測與模式
    (2015)
    汪大暉
    ;
    WANG TAHUI
    ;
    國立交通大學電子工程學系及電子研究所
    在奈米元件内，由於元件具有強烈的三度空間效應，通道内電場與local strain均具不均勻性， 元件内各個trap可因位置不同而對元件Vt有不同之影響，各個trap亦可因活化能不同或所在位置 電場不同而具有不同之時間常數。相較於大面積元件内元件退化特性是眾多trap之平均結果，在 奈米尺度元件内，每個元件可能僅含有一顆或少數顆trap，此時各個trap之差異性將逐漸顯現， 而導致奈米元件特性退化AVt呈現一較寬的分佈。在實際應用上，通常係AVt分佈之tail部分導 致元件與電路無法正常工作，本計劃的目的即在於研究元件内trap特性之統計分佈並建立元件退 化特性分佈之統計模式。 本計劃將研究VLSI元件三項重要單電荷(或少數顆電荷)效應所造成之可靠性議題，分別為 (a)奈米CMOS元件内AC BTI stress所造成AVt之統計分佈（b)奈米線電晶體内RTN之振幅分佈及 (c)a-粒子入射對於SONOS Vt分佈的影響。在BTI方面，吾人將測量數百顆high-k CMOS介電層 内trapped charge產生或釋放之時間常數，研究其分佈特性並粹取high-k trap活化能分佈及探討活 化能與元件結構，high-k/IL製程及通道材料之關係。並建立在AC BTI stress下元件退化AVt之統 計分佈模式。在RTN方面，將由平面式元件擴展至奈米線元件，利用3D數值模擬及吾人已自行 發展完成之量子線蒙地卡羅模擬研究奈米線元件内RTN之振幅分佈及理論模型。吾人並將以 FinFET近似奈米線元件量測RTN振幅分佈。在輻射線對SONOS可靠性方面，由於SONOS内電 荷儲存方式與理論與傳統快閃式元件不同，吾人將研究a-粒子照射對512Mb SONOS記憶體Vt 分佈之影響，並建立Vt分佈統計模型，此模型將包括儲存電荷因Frenkel-Poole emission而流失及 a-粒子照射兩種機制所造成之Vt distribution tail。
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    Impact of V-pass Interference on Charge-Trapping NAND Flash Memory Devices
    (2015-06-01)
    Hsiao, Yi-Hsuan
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    Lue, Hang-Ting
    ;
    Chen, Wei-Chen
    ;
    Chang, Kuo-Pin
    ;
    Tsui, Bing-Yue
    The impact of adjacent word-line\'s pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.
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    奈米SONOS元件內單電子效應、可靠性物理及創新研究
    (2010)
    汪大暉
    ;
    WANG TAHUI
    ;
    國立交通大學電子工程學系及電子研究所
    非揮發性記憶體技術，隨著各種新式電子產品應用與龐大需求，已邁入100Gb 儲存之奈米世 代。在各種研發之非揮發性記憶體技術(例如, SONOS, PCM, RRAM,…)中，SONOS 已被公認為最 具可能取代傳統浮動閘極快閃式元件之下一世代記憶體技術。目前SONOS 元件已微縮至奈米尺 度, NOR-type SONOS 已微縮至50 奈米，二位元儲存，而NAND-type SONOS 已達42 奈米，隨著 技術繼續演進，無論在元件物理，元件結構與材料，新式操作方法及記憶體架構各方面，均將面 臨重大挑戰。本計劃將針對奈米SONOS 微縮時之新的物理機制與效應及創新方法，進行為期三 年之研究，內容將涵蓋基本元件理論，元件雜訊random telegraph noise(RTN)，單電子效應及其隨 機特性，蒙地卡羅電子傳輸模擬，及新式元件結構與記憶體架構。主要研究議題，敘述如下； 在 NOR-type SONOS 方面，由於採用熱電子寫入，以致於寫入時操作電壓無法低於3.5V 而 限制閘極長度之微縮。在本計劃，吾人將利用在奈米尺度電子呈現之非平衡傳輸現象，提出一種 新的熱電子操作方式，可將寫入時的操作電壓降至2.5V 以下。NOR-type SONOS 微縮時，另一物 理限制為熱電子寫入時，會經由二次電子(secondary hot electron)之產生而在鄰近元件造成干擾 (program disturb)，此種效應在bitline 微縮時，將愈益明顯，吾人將利用蒙地卡羅模擬研究此種機 制並試圖提出解決方法。此外，當元件微縮時，單一電子效應將更為顯著，單單一顆介面電荷 (interface charge)或儲存電荷(nitride charge)釋放即可能造成讀取錯誤，前者即為RTN，已被廣泛視 為40 奈米以下NAND Flash 之主要可靠性議題。而後者尚未有人報導，吾人將建立一量測技術， 以測量此種單電子效應，觀察其隨機性，並進行理論研究，藉由3D 數值模擬，建立此種單電子 效應之統計模型並決定採用error code correction 時所需位元數。吾人將探討此種單電子效應與元 件結構之關係，並提出一具有高度對稱性之元件結構，以降低此種單電子效應所造成讀取錯誤之 機率。
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    新式非揮發性記憶體元件之研究(I)
    (2005)
    荊鳳德
    ;
    CHIN ALBERT
    ;
    交通大學電子工程系
    在矽超大型積體電路（VLSI）元件的研究方面中，除了互補式金氧半場 效電晶體元件（CMOS）外，記憶體元件（Memory）的發展也已成為另一主流。 半導體記憶體元件可區分為揮發性（Volatile）及非揮發性（Non-volatile）記憶 體兩種。若電源關閉時，揮發性記憶體如動態隨機存取記憶體（Dynamic Random Access Memory，DRAM），以及靜態隨機存取記憶體（Static Random Access Memory，SRAM ），將會失去所儲存的資料：而另一方面，非揮發性記憶體卻 可持續保持所儲存的資料。目前，動態隨機存取記憶體及靜態隨機存取記憶體被 廣泛的使用在個人電腦，而非揮發性記憶體則大量的應用在行動或攜帶式電子產 品中。由於非揮發性記憶體元件為單一電晶體結構（1T），其較動態隨機存取記 憶體具有節省單元面積（Cell Area）的功效以增加積集度，所以擁有非常好的潛 力去取代具有一個電晶體和一個電容（1T1C）結構的傳統式動態隨機存取記憶 體。本實驗室研究群即是希望能發展出新世代的單一電晶體記憶體或其他記憶體 元件以應用於動態隨機存取記憶體中。 其次，在非揮發性記憶體元件的領域中，除了以浮停閘當作電荷儲存層的 快閃式記憶體元件外（Flash Memory），還有一具有電荷捕捉層結構的元件，即 所謂的多晶矽-二氧化矽-氮化矽-二氧化矽-矽記憶體（Si-SiO2-Si3N4-SiO2-SiSONOS Memory）。一般快閃式記憶體由於浮停閘的熱載子（Hot Carrier）問題， 需有較長的抹除時間（Erase Time）以及需較厚的穿遂氧化層已維持良好的電荷 儲存能力（Retention），所以造成元件難以縮微到奈米尺寸，此外，閃式記憶體 必需操作在較高的編碼（Program）和抹除電壓下（電場超過6MV/cm）。因此近 年來，由於SONOS 結構可以解決平面微縮的問題、具有良好電荷儲存能力的特 性、低工作電壓以及符合目前互補式金氧半場效電晶體元件的製程，已開始受到 大家的關注。本實驗室研究群也將應用之前豐富的製程經驗和技術投入到此領 域，由於之前已與加拿大國立研究中心一起合作記憶性電容元件。因此在本計畫 中，我們將繼續互相合作，期望能結合雙方的優點，增進研究的深度與廣度，並 能集思廣益，在此領域研發出更快速，低工作電壓、高電荷儲存能力且符合微縮 的新式SONOS 結構記憶體。此外，我們在此計畫中也將與英國劍橋大學(註： 英國劍橋大學為目前全世界大學排名第六)的Dr. John Robertson 合作（附件一）， Dr. John Robertson 主要的研究領域為高介電係數介電質材料及能帶結構分析，由 於這項合作的促成，我們將得到一個非常有利且具有實質上的幫助。而且我們也 將與Prof. Hiroshi Iwai (President of IEEE Electron Device Society) 一起合作（附件 2）。Iwai 教授日前有一個Plenary Section Talk 在International Electron Devices Meeting (IEDM)，同時他也是一個擁有IEEE Erbers 獎的得主，他在high-k 及記 憶體方面的研究屬於全世界數一數二的學者。最後，此計畫也將由國立交通大學 張俊彥校長及電資學院吳重雨院長所共同協助指導與背書，因為與國際知名大學 的合作一直以為台灣所追求的目標。
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    High-Performance Bottom-Gate Poly-Si Polysilicon-Oxide-Nitride-Oxide-Silicon Thin Film Transistors Crystallized by Excimer Laser Irradiation for Two-Bit Nonvolatile Memory Applications
    (2012-07-01)
    Lee, I-Che
    ;
    Kuo, Hsu-Hang
    ;
    Tsai, Chun-Chien
    ;
    Wang, Chao-Lung
    ;
    Yang, Po-Yu
    High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm(2)/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.