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Subject: search.filters.subject.Schottky barrier

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Now showing 1 - 10 of 16
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    Reduction of Contact Resistivity by Nano-Textured Contact
    (1970-01-01)
    Tsui, Bing-Yue
    ;
    Lee, Ya-Hsin
    ;
    Lee, Chen-Yi
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The feasibility of reducing contact resistance by adding nano-textures on the contact surface is evaluated by three-dimensional simulation. Upward and downward pyramids and hemispheres are considered, and the effects of contact area and electric field are discussed. The downward nano-texture has a stronger electric field than the upward nano-texture; thus the increasing contact area will be more effectively used and lead to a greater improvement effect. On the other hand, the electric field of the hemisphere nano-texture is lower than that of the pyramid nano-texture. With proper design, the nano-textured contact can effectively reduce contact resistance up to 30-50%. Therefore, the proposed nano-textured contact is a promising approach with contact resistivity approaching physical limits.
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    Ultralow Schottky Barriers in Hexagonal Boron Nitride-Encapsulated Monolayer WSe2 Tunnel Field-Effect Transistors
    (2020-04-22)
    Pande, Gaurav
    ;
    Siao, Jyun-Yan
    ;
    Chen, Wei-Liang
    ;
    Lee, Chien-Ju
    ;
    Sankar, Raman
    To explore the potential of field-effect transistors (FETs) based on monolayers (MLs) of the two-dimensional semiconducting channel (SC) for spintronics, the two most important issues are to ensure the formation of variable low-resistive tunnel ferromagnetic contacts (FCs) and to preserve intrinsic properties of the SC during fabrication. Large Schottky barriers lead to the formation of high resistive contacts, and methods adopted to control the barriers often alter the intrinsic properties of the SC. This work aims at addressing both issues in fully encapsulated ML WSe2 FETs using bilayer hexagonal boron nitride (h-BN) as a tunnel barrier at the FC/SC interface. We investigate the electrical transport in ML WSe2 FETs with the current-in-plane geometry that yields hole mobilities of similar to 38.3 cm(2) V-1 s(-1) at 240 K and on/off ratios of the order of 10(7), limited by the contact regions. We have achieved an ultralow effective Schottky barrier (similar to 5.34 meV) with an encapsulated tunneling device as opposed to a nonencapsulated device in which the barrier heights are considerably higher. These observations provide an insight into the electrical behavior of the FC/h-BN/SC/h-BN heterostructures, and such control over the barrier heights opens up the possibilities for WSe2-based spintronic devices.
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    Graphene-Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits
    (2020-01-01)
    Yeh, Chao-Hui
    ;
    Liang, Zheng-Yong
    ;
    Lin, Yung-Chang
    ;
    Chen, Hsiang-Chieh
    ;
    Fan, Ta
    The most pressing barrier for the development of advanced electronics based on two-dimensional (2D) layered semiconductors stems from the lack of site-selective synthesis of complementary n- and p-channels with low contact resistance. Here, we report an in-plane epitaxial route for the growth of interlaced 2D semiconductor monolayers using chemical vapor deposition with a gas-confined scheme, in which patterned graphene (Gr) serves as a guiding template for site-selective growth of Gr-WS2-Gr and Gr-WSe2-Gr heterostructures. The Gr/2D semiconductor interface exhibits a transparent contact with a nearly ideal pinning factor of 0.95 for the n-channel WS2 and 0.92 for the p-channel WSe2. The effective depinning of the Fermi level gives an ultralow contact resistance of 0.75 and 1.20 k Omega.mu m for WS2 and WSe2, respectively. Integrated logic circuits including inverter, NAND gate, static random access memory, and five-stage ring oscillator are constructed using the complementary Gr-WS2-Gr-WSe2-Gr heterojunctions as a fundamental building block, featuring the prominent performance metrics of high operation frequency (>0.2 GHz), low-power consumption, large noise margins, and high operational stability. The technology presented here provides a speculative look at the electronic circuitry built on atomic-scale semiconductors in the near future.
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    A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications
    (1970-01-01)
    Lin, Che-Yi
    ;
    Chen, Chao-Fu
    ;
    Chang, Yuan-Ming
    ;
    Yang, Shih-Hsien
    ;
    Lee, Ko-Chun
    Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3Ge/Ge/Cu3Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 10(5) and 10(3) for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.
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    極低蕭基位障與接觸電阻技術之研究(I)
    (2010)
    崔秉鉞
    ;
    Tsui Bing-Yue
    ;
    國立交通大學電子工程學系及電子研究所
    隨金氧半場效電晶體的尺寸不斷微縮，金屬與源極/汲極的接觸面積也持續縮小， 接觸電阻在整體電晶體的寄生電阻中所佔的比例將會持續上升。欲降低接觸電阻係 數，必須提高接面載子濃度以及降低蕭基位障接面高度。然載子濃度受限於製程溫度 及元素在基板中的固態溶解度，除非更換基板材料，不容易再提高，降低蕭基位障高 度便成為當務之急。 本三年期計畫包含四個部分：極低蕭基位障高度的參數擷取與製程技術、極低接觸 電阻係數的參數擷取與製程技術、三維物性/化性/模擬分析技術、低寄生電阻奈米電晶 體整合技術。 第一年度以建立極低蕭基位障高度以及極低接觸電阻係數的參數擷取技術為主，以 便驗證後續製程技術開發的成效。本年度並將完成蕭基位障元件製作以及接觸電阻係數 的測試結構的設計，並嘗試幾種降低蕭基位障高度的技術。第二年度將延續第一年的進 度，尋求將蕭基位障高度降低到0.4eV 以下，接觸電阻係數3 Ω-μm2 以下的材料與製程 技術，並對各種製程的調變機制進行深入的理論分析。第三年度將整合前兩年度所發展 的低蕭基位障高度以及低接觸電阻技術於奈米尺度電子元件之製作，以驗證降低接觸電 阻對於提升元件性能的作用。 本計畫可以產出蕭基位障高度低於0.4eV、接觸電阻係數低於3 Ω-μm2 的材料與製 程技術，並在30nm 以下的電晶體驗證。此計畫規格符合2007 年ITRS 預估的2016 年 需求，極具學術與產業應用價值。
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    肖基障金氧半場效体之數值模擬
    (2001)
    郭雙發
    ;
    國立交通大學電子工程學系
  • Thumbnail Image
    Item type:Item,
    稀磁性半導體薄膜光學特性之研究與半導體微結構之理論探討(II)
    (1996)
    褚德三
    ;
    CHUU DER SAN
    ;
    國立交通大學電子物理學系
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    The effects of growth temperature on the microstructure and electrical barrier height in PtSi/p-Si(100) Schottky barrier detector
    (2000-10-03)
    Horng, GJ
    ;
    Chang, CY
    ;
    Ho, C
    ;
    Lee, CY
    ;
    Huang, TY
    The effects of growth temperature on the microstructure and electrical barrier height of the PtSi Schottky barrier detector (SBD) have been investigated. PtSi films, 4 nm in thickness were deposited at various temperatures ranging from 350 to 550 degreesC. The electron diffraction patterns showed that PtSi film formed at 350 degreesC depicts an intermingling of both (1 (1) over bar1) and (1 (2) over bar1) orientations. However, only (1 (2) over bar1) orientation was shown when the PtSi films were formed above 450 degreesC. Moreover, SBD formed at 350 degreesC was found to depict an electrical barrier that is approximately 0.02 eV higher than those formed above 450 degreesC. Although the microstructure and the electrical barrier height of the PtSi film do not change when the formation temperature was further increased from 450 to 550 degreesC. Nevertheless, the higher formation temperature resulted in a larger grain size, indicating that grain size alone does not affect the barrier height of the resultant SBD. (C) 2000 Elsevier Science S.A. All rights reserved.
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    Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension
    (2001-04-01)
    Lin, HC
    ;
    Yeh, KL
    ;
    Huang, RG
    ;
    Lin, CY
    ;
    Huang, TY
    A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on-off current ratio, the new device exhibits high on/off current ratio up to 10(6) for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
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    Ambipolar Schottky-barrier TFTs
    (2002-02-01)
    Lin, HC
    ;
    Yeh, KL
    ;
    Huang, TY
    ;
    Huang, RG
    ;
    Sze, SM
    A novel Schottky-barrier metal-oxide-semiconductor thin-film transistor (SBTFT) was successfully demonstrated and characterized. The new SBTFT device features a fleld-induced-drain (FID) region, which is controlled by a metal field-plate lying on top of the passivation oxide. The FED region is sandwiched between the silicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. The device is thus capable of ambipolar operation. Excellent ambipolar performance with on/off current ratios over 10(6) for both p- and n-channel operations was realized simultaneously on the same device fabricated with polysilicon active layer. Moreover, the off-state leakage current shows very weak dependence on the gate-to-drain voltage difference with the FID structure. Finally, the effects of FED length are explored.