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Subject: search.filters.subject.SiGe

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Now showing 1 - 10 of 33
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    Improving Photoelectric Energy Conversion by structuring Si Surfaces with Ge Quantum Dots
    (2019-01-01)
    Shmid, Volodymyr
    ;
    Kuryliuk, Vasyl
    ;
    Nadtochiy, Andriy
    ;
    Korotchenkov, Oleg
    ;
    Li, Pei-Wen
    Structuring Si surfaces with Ge quantum dots can have a beneficial effect on the photovoltage (PV), increasing the PV magnitude and decay time. The origin of this behavior is intimately related to mechanical strains developed in the vicinity of the Ge/Si interface. The structuring is a promising means of avoiding the uncontrolled production of recombination centers and offering significant enhancement of the recombination lifetime due to carrier trapping in the dots. This work can open new opportunities for advanced photoelectric devices with recombination center free nanostructures.
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    Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors
    (2016-02-11)
    Lai, Wei-Ting
    ;
    Yang, Kuo-Ching
    ;
    Liao, Po-Hsiang
    ;
    George, Tom
    ;
    Li, Pei-Wen
    We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGe-shell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 x 10(11) cm(-2) eV(-1) and fixed charge densities of 1-5 x 10(11) cm(-2), suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
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    Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
    (1998-02-01)
    Chen, LP
    ;
    Chan, YC
    ;
    Chang, SJ
    ;
    Huang, GW
    ;
    Chang, CY
    Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
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    Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices
    (2018-05-18)
    Liao, P. H.
    ;
    Peng, K. P.
    ;
    Lin, H. C.
    ;
    George, T.
    ;
    Li, P. W.
    We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5-95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5-4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1-xGex shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1-xGex shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices.
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    260-GHz differential amplifier in SiGe heterojunction bipolar transistor technology
    (2017-02-02)
    Yoon, D.
    ;
    Seo, M. -G.
    ;
    Song, K.
    ;
    Kaynak, M.
    ;
    Tillack, B.
    A 260-GHz amplifier in a SiGe heterojunction bipolar transistor (HBT) technology is reported. It is based on three-stage differential cascode topology and adopts a passive shunt transistor pair at the output of each amplifying stage to relax instability caused by parasitic base inductance of amplifying transistor pair. The instability of the amplifier can be mitigated by tuning the base bias voltage of the shunt transistor pair. Peak gain of the amplifier was measured as 15 dB at 260 GHz. DC power dissipation is 112 mW. The chip occupies 300 x 160 m(2) excluding Baluns and probing pads.
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    矽鍺源/汲極金氧半電晶體及電感在射頻應用之研究(I)
    (2000)
    張俊彥
    ;
    CHANG CHUN-YEN
    ;
    交通大學電子工程系
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    矽與矽鍺材料及元件之發展---總計畫
    (1997)
    張俊彥
    ;
    CHANG CHUN-YEN
    ;
    交通大學電子工程研究所
    本整合計畫將以三年的時間，研究探討Si及SiGe磊晶層之成長機制，摻雜特性。SiGe之材料及物理特性，包括成長Si/ SiGe量子井(QuantumnWell)及超晶格(Super-lattice)等結構材料，並藉由SIMS、X-Ray Diffraction、 RBS、TEM 、SEM、 AFM及FTIR等儀器分析材料及物理特性.以此為基礎，我們將研製短通道 Si及SiGeMOSFET元件和異質接面雙極性電晶體HBT。最後，我仍將分析SiGe MOSFET和SiGeHBT的直流高頻特性，並與SiMOSFET和BJT作比較，以驗證矽鍺材料的物理特性及其在半導體元件物理應用的潛力。經由此計畫的進行，我們將能夠對於Si/SiGe磊晶層，從成長、材料特性、物理特性、量測技術、元件製作、到電路的應用，有一完整的研究。對於未來 Si/SiGe材料的發展有很重大的意義。
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    Item type:Item,
    Direct oxidation of Si1-xGex layers using Vacuum-Ultra-Violet light radiation in oxygen
    (1998-02-01)
    Chen, LP
    ;
    Chan, YC
    ;
    Chang, SJ
    ;
    Huang, GW
    ;
    Chang, CY
    Oxidation of Si1-xGex films has been carried out by direct photo chemical Vapor deposition (direct photo-CVD) directly with activated O-2 induced by Vacuum-Ultra-Violet (VUV) light radiation, The Auger electron spectroscopy profiles show that no Ge-pileup layer at the oxide/Si1-xGex interface is observed after VUV-induced Si1-xGex oxidation process. The X-ray photoelectron spectroscopy analysis of the samples reveals that Si and Ge are oxidized simultaneously in oxidation process and a mixed oxide layer consisting both SiO2 and GeO2 is formed, This might be the reason that Cc pileup effect is eliminated in this study.
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    Nanogrids and Beehive-Like Nanostructures Formed by Plasma Etching the Self-Organized SiGe Islands
    (2010-09-01)
    Chang, Yuan-Ming
    ;
    Jian, Sheng-Rui
    ;
    Juang, Jenh-Yih
    ;
    電子物理學系
    ;
    Department of Electrophysics
    A lithography-free method for fabricating the nanogrids and quasi-beehive nanostructures on Si substrates is developed. It combines sequential treatments of thermal annealing with reactive ion etching (RIE) on SiGe thin films grown on (100)-Si substrates. The SiGe thin films deposited by ultrahigh vacuum chemical vapor deposition form self-assembled nanoislands via the strain-induced surface roughening (Asaro-Tiller-Grinfeld instability) during thermal annealing, which, in turn, serve as patterned sacrifice regions for subsequent RIE process carried out for fabricating nanogrids and beehive-like nanostructures on Si substrates. The scanning electron microscopy and atomic force microscopy observations confirmed that the resultant pattern of the obtained structures can be manipulated by tuning the treatment conditions, suggesting an interesting alternative route of producing self-organized nanostructures.
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    High temperature formed SiGeP-MOSFET's with good device characteristics
    (2000-07-01)
    Wu, YH
    ;
    Chin, A
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We have used a simple process to fabricate Si0.3Ge0.7/Si p-MOSFET's. The Si0.3Ge0.7 is formed using deposited Ge followed by 950 degrees C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. Hole mobility of 250 cm(2)/Vs is obtained from Si0.3Ge0.7 p-MOSFET that is similar to two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Angstrom Si0.3Ge0.7 thermal oxide grown at 1000 degrees C has a high breakdown field of 15 MV/cm, low interface trap density (D-it) of 1.5 x 10(11) eV(-1) cm(-2), and low oxide charge of 7.2 x 10(10) cm(-2). The source-drain junction leakage after implantation and 950 degrees C RTA is also comparable with Si counterpart.