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Now showing 1 - 8 of 8

An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
(2019-05-01)
Liu, Chi-Wei
;
Chen, Yi-Lun
;
Liao, Pei-Chun
;
Lin, Shiau-Pin
;
Wang, Ting-Wei
This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
A Single-Inductor Dual-Ouput (SIDO) DC-DC Converter for Implantable Medical Devices in 180nm Standard CMOS Process
(2018-01-01)
Liao, Pei-Chun
;
Chen, Yi-Lun
;
Chen, Po-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a single-inductor dual-output (SIDO) buck converter is developed for implantable medical devices. The stacked power stage with startup circuit is designed to avoid over-stress issue in 180nm CMOS process for 3.4 V to 5 V battery input. The converter provides two regulated outputs for the charge pump (V-OUT1 = 3 V) and the digital circuits (V-OUT2 = 2 V) with low cross regulation with pulse-skip modulation. An adaptive on-time (AOT) circuit adjusts on time dynamically based on the input voltage (V-IN) to obtain high conversion efficiency and low output voltage ripple under different V-IN. The measurement results demonstrates that the proposed converter achieves peak efficiency of 93.6% with an available input voltage of 3.4 V to 5 V.
Automatic Mode-Selected Energy Harvesting Interface With > 80% Power Efficiency Over 200 nW to 10 mW
(2018-12-01)
Chen, Po-Hung
;
Cheng, Hao-Chung
;
Ai, Yi-An
;
Chung, Wang-Ting
;
電子工程學系及電子研究所
This paper proposes a dual-mode digital buck converter with an automatic mode-select feature in a 0.18-mu m CMOS for self-powered Internet-of-Things applications. The proposed converter combines the digital pulsewidth modulation and the proposed predetermined pulse-frequency modulation (PPFM) techniques to achieve both a high conversion efficiency and a wide output power range. The proposed PPFM technique calculates the appropriate OFF time of the power transistor in advance, eliminating the additional power budget requirement of the conventional zero-crossing detection circuit. From the results, it can be seen that the conversion efficiency improves by 21% under ultralight-load conditions. The available input voltage (V-IN) ranges from 0.55 to 1.8 V for a wide variety of energy harvesters, and the output voltage (V-OUT) ranges from 0.3 to 0.55 V to power the energy-efficient CMOS digital circuits. The proposed dual-mode digital buck converter achieves a maximum conversion efficiency of 90.5%, with an output power ranging from 25 nW to 10 mW. Owing to the proposed PPFM technique, the converter achieves a power conversion efficiency of more than 80%, with an output power of 200 nW to 10 mW.
A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
(2016-02)
Chen, Po-Hung
;
Wu, Chung-Shiang
;
Lin, Kai-Chun
;
交大名義發表
;
National Chiao Tung University
This paper presents a tri-mode digital buck converter in 0.18-mu m CMOS technology for photovoltaic energy harvesting. The on-chip gate-boosted digital pulsewidth modulation (DPWM) improves the conversion efficiency at heavy load conditions. Pulse-frequency modulation (PFM) along with digital self-tracking zero current detection is proposed to avoid reverse current at light load. The asynchronous mode (AM) operation further reduces the controller loss and improves the conversion efficiency at ultra-light load conditions. By applying DPWM, PFM, and AM at different load conditions, the proposed converter provides a maximum conversion efficiency of 92% with output power ranging from 50 nW to 10 mW. In addition, the proposed buck converter achieves more than 70% efficiency from 400 nW to 10 mW output power.
Implantable Biomedical Device Supplying by a 28nm CMOS Self-Calibration DC-DC Buck Converter with 97% Output Voltage Accuracy
(2015)
Yang, Te-Fu
;
Huang, Ru-Yu
;
Su, Yi-Ping
;
Balakumar
;
Chen, Ke-Horng
Implantable devices like artificial cardiac pacemakers are generally used to control irregular pulses of heart. For 10-year usage, high accuracy supply voltage is essential with the unavoidable aging of the power system to achieve near-natural beat rhythm. A Self-Calibration DC-DC Buck converter (SC-Buck) is proposed to achieve high output voltage accuracy by eliminating offset caused by mismatch of process, voltage and temperature (PVT). Furthermore, the discontinuity which affects transient performance in conventional offset cancellation is also overcome. Large area occupation, which is required to decrease mismatch in conventional operational amplifier, can be largely decreased according to Monte Carlo analysis. Without trimming process, the proposed SC-Buck technique achieves high accuracy for long-term usage (years) and low cost. The test chip fabricated in UMC 28nm CMOS process proves the output voltage accuracy of 97% since the mismatch of error amplifier can be suppressed from 122% to 1%.
Fast Mode-Switching Technique in Hrbrid-Mode Operation
(2008)
Chen, Chi-Lin
;
Hsieh, Wei-Lun
;
Huang, Han-Hsiang
;
Chen, Ke-Horng
;
電控工程研究所
A fast mode-switching technique between pulse width modulation (PWM) and pulse frequency modulation (PFM) modes Is proposed to keep high efficiency over wide load range. Load dependent zero-current detector (ZCD) can effectively speed up the transition from PWM to PFM mode. Especially, the overshoot voltage can be minimized by using the reversed current provided by the ZCD circuit. Furthermore, the undershoot voltage of the transition from PFM to PWM mode can be reduced because the recovery time can be reduced by restoring the output voltage of the error amplifier. Thus, the efficiency of current mode DC-DC buck converter is higher than 88% at light loads and the recovery time is smaller than 35 mu s when load current changes from 500mA to 10mA suddenly.
Zero current detection technique for fast transient response in buck DC-DC converters
(2008)
Chen, Chi-Lin
;
Lai, Wei-Jen
;
Liu, Ter-Hsing
;
Chen, Ke-Horng
;
電控工程研究所
A load dependent zero-current detector is proposed in this paper for speeding up the transient response when load current changes from heavy to tight loads. The fast transient control signal determines how long the reversed inductor current according to sudden load variations. At the beginning of load variation from heavy to tight loads, the sensed voltage compared with higher voltage to discharge the overshoot output voltage for achieving fast transient response. Besides, for an adaptive reversed current period, the fast transient mechanism is turned off since the output voltage is rapidly regulated back to the acceptable level. Simulation results demonstrate that the ZCD circuit permits the reverse current flowing back into n-type power MOSFET at the beginning of load variations. The settling time is decreased to about 35 mu s when load current suddenly changes from 500mA to 10 mA.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
;
Hsieh, Chun-Yu
;
Yang, Yao-Yi
;
Lee, Yu-Huei
;
Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.

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