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Subject: search.filters.subject.coupling coefficient

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Now showing 1 - 3 of 3
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    A microstrip elliptic function filter with compact miniaturized hairpin resonators
    (2000-03-01)
    Kuo, JT
    ;
    Maa, MJ
    ;
    Lu, PH
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    A four-pole elliptic function bandpass filter is designed using compact miniaturized microstrip hairpin resonators. It is shown that the filter occupies a very small area. The full-wave simulator IE3D is used to design the resonator and to calculate the coupling coefficients of the three basic coupling structures. Measurement results are compared with the computed responses.
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    Miniaturized 3-dimensional transformer design
    (2005)
    Chen, WZ
    ;
    Hsu, KC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    3-dimentional fully-symmetric transformers are proposed and realized in a standard CMOS technology. In contrast to their planar counterparts, the self resonant frequency (f(SR)) of the proposed architecture is improved by 26 % to 53 %, while the chip area is reduced by 40 % to 70 %. The coupling coefficient (K) can be up to 0.77 at 8 GHz in a two turn two layer architecture. Distributed capacitance model (DCM) of the 3-D transformer is also proposed f(SR) evaulation.
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    Three-dimensional fully symmetric inductors, transformer, and balun in CMOS technology
    (2007-07-01)
    Chen, Wei-Zen
    ;
    Chen, Wen-Hui
    ;
    Hsu, Kuo-Ching
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presents novel three-dimensional (3-D) symmetric passive components, including inductors, transformers, and balun. Layout areas of these components are drastically reduced by 32% to 70%, while the symmetry of the input and the output ports is still maintained. The inductance mismatch in the 3-D transformer is less than 0.1%, and the coupling coefficient can be up to 0.77. The 3-D balun manifests less than 0.6-dB gain mismatch for 10-GHz range, and the phase error is less than 7 degrees from 1- to 10-GHz frequency range according to measurement results. Furthermore, the self-resonant frequency (f(SR)) of the proposed architecture is improved by 32% to 61% in contrast to their planar counterparts. On the other hand, the quality factor is degraded by less than 2 for the sake of using lower metal layers. The distributed capacitance model is utilized to validate their superiorities in f(SR). All the devices are fabricated in a generic 0.18-mu m CMOS process.