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Subject: search.filters.subject.dielectric breakdown

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Now showing 1 - 9 of 9
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    Evaluation of plasma charging damage in ultrathin gate oxides
    (1998-03-01)
    Lin, HC
    ;
    Chen, CC
    ;
    Chien, CH
    ;
    Hsein, SK
    ;
    Wang, MF
    Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 nm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.
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    Improved immunity to plasma damage in ultrathin nitrided oxides
    (2000-01-01)
    Chen, CC
    ;
    Lin, HC
    ;
    Chang, CY
    ;
    Liang, MS
    ;
    Chien, CH
    Plasma-induced damage in various 3-nm thick gate oxides (i.e., pure O-2 and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition, Gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as at the wafer edge for pMOS devices, while it occurs only at the wafer center for nMOS devices, These interesting observations could be explained by the polarity dependence of ultrathin oxides in charge-to-breakdown measurements. Additionally, ultrathin N2O-nitrided oxides show superior immunity to charging damage, especially for pMOS devices.
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    Plasma-induced charging damage in ultrathin (3-nm) gate oxides
    (2000-07-01)
    Chen, CC
    ;
    Lin, HC
    ;
    Chang, CY
    ;
    Liang, MS
    ;
    Chien, CH
    Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-break-down and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra-thin oxides in charge-to breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between n- and p-MOSFET,s. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N2O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides.
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    Physical and barrier properties of plasma-enhanced chemical vapor deposited alpha-SiCN : H films with different hydrogen contents
    (2003-08-01)
    Chiang, CC
    ;
    Chen, MC
    ;
    Ko, CC
    ;
    Jang, SM
    ;
    Yu, CH
    This work investigates the thermal stability and physical and barrier properties of two species of plasma-enhanced chemical-vapor-deposited (PECVD) amorphous silicon-nitrocarbide (alpha-SiCN:H) films with different hydrogen contents and dielectric constants of less than 5. It is found that the alpha-SiCN:H film with a higher hydrogen content has a lower dielectric constant. Both species of alpha-SiCN:H films are thermally stable at temperatures up to 500degreesC. However, a degraded dielectric strength was observed for the alpha-SiCN:H film with a lower k-value of 4, which has a much higher hydrogen content. This may be attributed to hydrogen-related defects, such as Si-H+-Si hydrogen bridges, and numerous Si-H weak bonds produced by the high hydrogen content in the alpha-SiCN:H film.
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    Effects of O-2- and N-2-plasma treatments on copper surface
    (2004-11-01)
    Chiang, CC
    ;
    Chen, MC
    ;
    Li, LJ
    ;
    Wu, ZC
    ;
    Jang, SM
    In this work, we investigate the effects of oxygen (O-2) and nitrogen (N-2) plasma treatments on the copper surface of aluminum/amorphous silicon-nitricarbide/copper (Al/alpha-SiCN/Cu) metal-insulator-metal (MIM) capacitors with respect to their leakage current and breakdown field. It is found that both the O-2- and N-2-plasma treatments have an adverse effect on the leakage current and breakdown field of MIM capacitors. The MIM capacitors with their Cu surfaces subjected to O-2- or N-2-plasma treatment exhibit a room-temperature leakage current density several orders of magnitude larger than that of the sample without plasma treatment at the same applied electric field. The room-temperature breakdown fields of the MIM capacitors with O-2- and N-2-plasma-treated Cu surfaces are 3.8 and 3.2 MV/cm, respectively, while that of the control sample without plasma treatment is 7.8MV/cm. The increased leakage currents and degraded breakdown fields of the O-2- and N-2-plasma-treated samples are attributed, respectively, to the presence of metastable Cu-O oxide and Cu-N azide at the Cu surfaces.
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    Influence of bias-temperature stressing on the electrical characteristics of SiOC : H film with Cu/TaN/Ta-gated capacitor
    (2006-07-01)
    Tsai, Kou-Chiang
    ;
    Wu, Wen-Fa
    ;
    Chao, Chuen-Guang
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    Experiments on bias-temperature stressing, capacitance-voltage measurements, current-voltage characteristics, and time-dependent dielectric breakdown were performed to evaluate the reliability of Cu and low-k SiOC:H integration. A high leakage current of similar to 8 X 10(-10) to 2 X 10(-8) A/cm(2) at 1 MV/cm in SiOC:H dielectrics in a Cu-gated capacitor, and a lower 2 X 10(-10) to 5 X 10(-10) A/cm(2) at 1 MV/cm in a Cu/TaN/Ta-gated capacitor, were observed at evaluated temperatures. The drift mobility of the Cu ions in the Cu/TaN/Ta-gated capacitor was lower than that in a Cu-gated capacitor. A physical model was developed to explain the observed kinetics of Cu+ ions that drift in Cu-gated and Cu/TaN/Ta-gated capacitors. The electric field in the Cu-gated MIS capacitor in the cathode region is believed to be increased by the accumulation of positive Cu+ ions, which determines the breakdown acceleration. Good Cu, ions drift barrier layers are required as reliable interconnects using thin TaN and Ta layers. Additionally, Schottky emission dominates at low electric fields, E < 1.25 MV/cm, and Poole-Frenkel emission dominates at high fields, E > 1.5 MV/cm.
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    The impact of gate-oxide breakdown on common-source-amplifiers with diode-connected active load in low-voltage CMOS processes
    (2007-11-01)
    Chen, Jung-Sheng
    ;
    Ker, Ming-Dou
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test. conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output dc voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the nonstacked diode-connected active-load structure are strongly degraded than that with the stacked diode-connected active-load structure due to a gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functionally operational under digital application due to the gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on the common-source amplifiers with nonstacked and stacked diode-connected active-load structures has been analyzed and discussed. The hard breakdown has more serious impact on the common-source amplifiers with diode-connected active load.
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    Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process
    (2008-03-01)
    Chen, Jung-Sheng
    ;
    Ker, Ming-Dou
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switched-capacitor circuit is investigated in this work with the sample-and-hold amplifier (SHA) in a 130-nm CMOS process. After overstress on the MOS switch of SHA with unity-gain buffer, the circuit performances in time domain and frequency domain are measured to verify the impact of gate-oxide reliability on circuit performances. The oxide breakdown on switch device degrades the circuit performance of bootstrapped switch technique.
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    Impact of MOSFET gate-oxide reliability on CMOS operational amplifier in a 130-nm low-voltage process
    (2008-06-01)
    Ker, Ming-Dou
    ;
    Chen, Jung-Sheng
    ;
    電機學院
    ;
    電子工程學系及電子研究所
    ;
    College of Electrical and Computer Engineering
    The effect of the MOSFET gate-oxide reliability on operational amplifier is investigated with the two-stage and folded-cascode structures in a 130-nm low-voltage CMOS process. The test operation conditions include unity-gain buffer (close-loop) and comparator (open-loop) configurations under the de stress, ac stress with dc offset, and large-signal transition stress. After overstress, the small-signal parameters, such as small-signal gain, unity-gain frequency, and phase margin, are measured to verify the impact of gate-oxide reliability on circuit performances of the operational amplifier. The gate-oxide reliability in the operational amplifier can be improved by the stacked configuration under small-signal input and output application. The impact of soft and hard gate-oxide breakdowns on operational amplifiers with two-stage and folded-cascode structures has been analyzed and discussed. The hard breakdown has more serious impact on the operational amplifier.