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A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices
(2020-08-01)
Lee, Yu-Chi
;
Chi, Tai-Shih
;
Yang, Chia-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
This article presents an acoustic DSP processor containing a neural network core for intelligent hearing assistive devices. The processor includes the accelerators for convolutional neural networks (CNNs) and fast Fourier transform (FFT). The CNN-based speech enhancement algorithm predicts the desired mask for the Fourier spectrogram of the speech signal to enhance speech intelligibility. Several design techniques are applied to enable efficient hardware mapping. The computational complexity for the CNN can be reduced by 23.6% by frame sharing, and a fast mask generation + partial sums pre-computation technique further reduces output latency by up to 64%. The size of the memory for the model is reduced by 75% using weight quantization. FFT is implemented by leveraging the packing algorithm to reduce the computational complexity by 43%. Reconfigurable processing elements are shared to support both FFT and CNN, realizing a saving in the area of 42%. In addition, input sharing and output sharing are used to, respectively, reduce data movements by 94% and 75%. A reordered FFT structure also eliminates up to 256 multiplexers. Fabricated in a 40-nm CMOS technology, the chip's core area is 4.2 mm(2) and the power dissipation is 2.17 mW at a clock frequency of 5 MHz from a 0.6-V supply. The embedded CNN accelerator supports both convolutional and fully connected (FC) layers and achieves a comparable energy efficiency with state-of-the-art CNN accelerators, despite the flexibility for FFT. The speech intelligibility is enhanced by up to 41% in the low SNR regime.
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices
(2019-01-01)
Lee, Yu-Chi
;
Chi, Tai-Shih
;
Yang, Chia-Hsiang
;
電機工程學系
;
Department of Electrical and Computer Engineering
This paper proposes an acoustic DSP processor with a neural network core for speech enhancement. Accelerators for convolutional neural network (CNN) and fast Fourier transform (FFT) are embedded. The CNN-based speech enhancement algorithm takes the speech signals spectrogram as the model's input, and predicts the desired mask of speech to enhance speech intelligibility after passing through the CNN model. An array of multiply-accumulator (MAC) and coordinate rotation digital computer (CORDIC) engines are deployed to efficiently compute linear and nonlinear functions. Hardware sharing is applied to reduce hardware area by leveraging the high similarity between CNN and FFT computations. The proposed DSP processor chip is fabricated in a 40-nm CMOS technology with a core area of 4.3 mm(2). The chip's power dissipation is 2.17 mW at an operating frequency of 5 MHz. The CNN accelerator supports both convolutional and fully-connected layers and achieves an energy efficiency of 1200-to-2180 GOPS/W, despite the flexibility for FFT. The speech intelligibility can be enhanced by up to 41% under low SNR conditions.
A 183-GHz InP/CMOS-Hybrid Heterodyne-Spectrometer for Spaceborne Atmospheric Remote Sensing
(2019-05-01)
Kim, Yanghyo
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Zhang, Yan
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Reck, Theodore James
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Nemchick, Deacon J.
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Chattopadhyay, Goutam
Acomplete 183-GHz CMOS/Indium Phosphide (InP) hybrid heterodyne-spectrometer is realized for spaceborne atmospheric remote sensing applications. It captures spontaneous emission from thermally populated pure rotational states for investigating Earth/planetary atmosphere and interstellar media. Recent missions such as the heterodyne instrument for far-infrared, the microwave limb sounder, and the microwave instrument for Rosetta orbiter highlighted the wealth of scientific knowledge that can be attained by utilizing heterodyne-spectrometers. However, major challenges still remain in mission cost, instrument size, weight, and power (SWaP). Highly integrated CMOS circuits are designed to prototype a low-cost/SWaP spectrometer system and conduct challenging science missions. Within the prototype system, a 183-GHz receiver with a frequency synthesizer is designed in the 28-nm CMOS, and a back-end 6-GS/s 4096-point spectrometer processor is designed in the 65-nm CMOS. The receiver's center frequency is tunable from 180 to 200 GHz. An external InP low-noise amplifier is added at the front-end to provide the required receiver sensitivity. The demonstrated 28-nm CMOS receiver and 65-nm CMOS spectrometer consume 515 mW under 1.5/1.15-V and 1500 mW under 1 V supply, respectively. The complete system achieves 700 to 1000 K noise temperature within the interested bandwidth and RMS uncertainty improvement up to 10 s integration according to the Allan deviation measurements. The spectrometer's capability in detecting gas phase molecular compounds is verified with laboratory trials employing water (H2O) and methyl-cyanide (CH3CN).
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
(2016-03)
Lai, Shin-Chi
;
Juang, Wen-Ho
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Lee, Yueh-Shu
;
Chen, Shin-Hao
;
Chen, Ke-Horng
This brief presents a hybrid structure to effectively compute the variable-length Fourier transform by employing the recursive and radix-2(2) fast algorithm. After applying a hardware-sharing scheme to both fast algorithms, the proposed method not only improves the drawback of higher hardware cost in implementation but also retains the regular and flexible nature of recursive discrete Fourier transform (RDFT). The proposed hardware accelerator only costs four real multipliers and ten real adders with a greater reduction (86.7% and 66.7%, respectively) than Kim et al.\'s design. In addition, the number of multiplications and additions for 256-point DFT computations can be reduced by 38.6% and 70%, respectively, compared to Lai et al.\'s recent approach. For accuracy analysis, the SNR value of the proposed design, at least, is 4 dB higher than the other RDFT designs. Considering a whole evaluation, a very-large-scale integration chip design was further fabricated using TSMC 0.18-mu m 1P6M CMOS process. The core size was only 660 x 660 mu m(2), and the measured power consumption was 8.8 mW @ 25 MHz. The result shows that the proposed chip included data memory is 1.38 times the computational efficiency per unit area of Lai et al.\'s work. Therefore, it will be the state-of-the-art RDFT processor in the application of various variable-transform-length digital signal processing issues.
A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems
(2008-05-01)
Chen, Yuan
;
Lin, Yu-Wei
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Tsao, Yu-Chi
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2(4) FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FITT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 x 1.88 mm(2). The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.
A dynamic scaling FFT processor for DVB-T applications
(2004-11-01)
Lin, YW
;
Liu, HY
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer 1 are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 4.84 mm(2). Power dissipation is about 25.2 mW at 20 MHz.
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
(2013-04-01)
Yang, Kai-Jiun
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Tsai, Shang-Ho
;
Chuang, Gene C. H.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-N-s butterflies at each stage, where N-s is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let N-s = 4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm(2). The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.
Design of an FFT/IFFT processor for MIMO OFDM systems
(2007-04-01)
Lin, Yu-Wei
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mu m single-poly and eight-metal CMOS process. The core area is 660 x 2142 mu m(2), including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mu s meeting IEEE 802.11n standard requirements.
An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications
(2008-02-01)
Chen, Yuan
;
Tsao, Yu-Chi
;
Lin, Yu-Wei
;
Lin, Chin-Hung
;
Lee, Chen-Yi
In this brief, a high-throughput and low-complexity fast Fourier transform (FFT) processor for wideband orthogonal frequency division multiplexing communication systems is presented. A new indexed-scaling method is proposed to reduce both the critical-path delay and hardware cost by employing shorter wordlength. Together with the mixed-radix multipath delay feedback structure, the proposed FFT processor can achieve very high throughput with low hardware cost. From analysis, it is shown that the proposed indexed-scaling method can save at least 11% memory utilizations compared to other state-of-the-art scaling algorithms. Also,,a-test chip of a 1.2 Gsample/s 2048-point FFT processor has been designed using UMC 90-nm 1P9M process with a core area of 0.97 mm(2). The signal-to-quantization-noise ratio (SQNR) performance of this test chip is over 32.7 dB to support 16-QAM modulation and the power consumption is about 117 mW at 300 MHz. Compared to the fixed-point FFT processors, about 26% area and 28% power can be saved under the same throughput and SQNR specifications.
Semi-parametric linear mixed effects model for vehicles identification
(2007)
Jou, Yow-Jen
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Yang, Chai-Tzu
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Huang, Chien-Chia
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Wu, Jennifer Yuh-Jen
;
資訊管理與財務金融系註：原資管所+財金所
In order to make the detecting of the lanes and the types of the vehicles traveling on various roadways affordable, radio-frequency (RF) system-on-chip is designed and will be mounted on the roadside to collect vehicle information. We use the Fast Fourier Transform (FFT) to transform the signal of the reflecting wave radar into the numerical data, and utilize it by the statistical approach to discriminate the size of cars and the lanes. In order to classify the types of the vehicles, two models are proposed to model the data. One is multivariate analysis of variance model to account for the main effect and the interaction effect between type and lane, the other is the semi-parametric linear mixed effect model to emphasize the functional characteristic of the data. Both models work well when the number of groups is small but deteriorate when the number of groups increases.

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