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A Flip-Chip-Assembled W-Band Receiver in 90-nm CMOS and IPD Technologies
(2019-04-01)
Li, Chun-Hsing
;
Hsieh, Wan-Ting
;
Chiu, Te-Yen
;
交大名義發表
;
National Chiao Tung University
A flip-chip-assembled W-band receiver composed of a 90-nm CMOS chip and an integrated-passive-device (IPD) carrier is presented in this paper. The chip which integrates a low-noise amplifier, a single-sideband mixer, a frequency doubler (FD), and a wide-band variable-gain amplifier, is flip-chip packaged to the IPD carrier through a low-loss interconnect. The simulated loss of the interconnect without any compensation network is only 0.95 dB at 94 GHz. The FD can provide differential output without any additional lossy balun required, effectively increasing the FD output power, and hence relaxing the local oscillator generation circuit design. The experimental results show that the proposed packaged receiver can provide a variable gain from 11.3 to 48.2 dB, while having an input 1-dB compression point from -43.7 to -29 dBm as the RF frequency is 90 GHz. The intermediate bandwidth and minimum noise figure can be 1.0 GHz and 7.8 dB, respectively. The proposed receiver only consumes 73.9 mW from a 1.2-V supply. As compared with prior works, the proposed receiver exhibits higher gain, lower noise, and lower power dissipation even though a less-advanced 90-nm CMOS technology is adopted. To the best of the authors' knowledge, this is the first W-band CMOS receiver assembled on an IPD carrier reported thus far.
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
(2012-06-01)
Ho, Yingchieh
;
Chen, Hung-Kai
;
Su, Chauchin
;
電子工程學系及電子研究所
;
電控工程研究所
This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).
Joint strength of Ag-9Pd-9Ga brazed interconnect and anode-supported electrolyte for solid-oxide fuel cell applications
(2018-09-01)
Chao, Chih-Long
;
Chu, Chun-Lin
;
Fuh, Yiin-Kuen
;
Hsu, Ray-Quen
;
Lee, Shyong
A newly developed Ag-9Pd-9Ga active filler was vacuum brazed, and the mechanical properties between the metallic interconnects (SS430, Crofer22 APU, Crofer22 H) and a Ni-yttria-stabilized zirconia cermet anode were systematically investigated. The results indicate that the bonding between metal and cermet is well established and that the interface is smooth. The joint strength evaluated at both 25? and 800? under shear and tensile loading conditions confirmed that the brazed Ag-9Pd-9Ga sealant compared favorably with its commercially available glass-ceramic GC-9 counterpart.
A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A Broadband Interconnect for THz Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Wu, Jan-Jr
;
Kuo, Chien-Nan
;
Cheng, Yu-Ting
;
Kuo, Ming-Ching
A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.
A Low-Cost Broadband Bondwire Interconnect for THz Heterogeneous System Integration
(2015)
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電機工程學系
A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.
Design of Flip-Chip Interconnect Using Epoxy-Based Underfill Up to V-Band Frequencies With Excellent Reliability
(2010-08-01)
Hsu, Li-Han
;
Wu, Wei-Cheng
;
Chang, Edward Yi
;
Zirath, Herbert
;
Hu, Yin-Chu
This study demonstrates a flip-chip interconnect with epoxy-based underfill (epsilon(r) = 3.5 and tan delta = 0.02 at 10 MHz) for packaging applications up to V-band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al(2)O(3) substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip interconnect showed excellent performance from dc to 67 GHz with return loss below -20 dB and insertion loss less than 0.6 dB. Furthermore, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 degrees C/85 % relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the S-parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
(2000-09-01)
Jiang, IHR
;
Chang, YW
;
Jou, JY
;
資訊工程學系
;
電子工程學系及電子研究所
Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which ran optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1-MB memory and 19.4-min runtime to achieve the precision of within 1% error on a SUN Spare Ultra-I workstation.
Effect of aluminum seed layer on the crystallographic texture and electromigration resistance of physical vapor deposited copper interconnect
(2000-12-01)
Chin, YL
;
Chiou, BS
;
Wu, WF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The effects of an Al underlayer with respect to texture control and electromigration (EM) resistance of Cu films are investigated in this study. The Al underlayer enhances the (111) texture of Cu films and the surface smoothness of the annealed Cu film. The same cubic crystal structure (face-centercd cubic) and small difference of the nearest interatomic distance of the (111) plane between Cu and Al result in the increase of the peak ratio I((111))/I-(200) of Cu films. The thicker the Al film, the more preferred the Cu (111) orientation. The resistivity of the Cu/AI bilayer film, which increases at about 0.2 mu Omega .cm per 1-nm-thick Al underlayer, is smaller than the reported value of single phase Cu(Al) solution. The EM resistance of Cu interconnects is also improved when the Al underlayer is present. The mean time to failure (MTF) of Cu interconnects with a 5-nm-thick Al underlayer is longer by one order of magnitude than that without an Al underlayer at 240 degreesC and 12 MA/cm(2).
Matching-based algorithm for FPGA channel segmentation design
(2001-06-01)
Chang, YW
;
Lin, JM
;
Wong, MDF
;
資訊工程學系
;
Department of Computer Science
Process technology advances have made multimillion gate field programmable gate arrays (FPGAs) a reality. A key issue that needs to be solved in order for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. Channel segmentation designs have been studied to some degree in much of the Literature; the previous methods are based on experimental studies, stochastic models, or analytical analysis, In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a problem of finding the optimal segmentation architecture for two input routing instances and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient multilevel matching-based algorithm for general channel segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves average improvements of 18.2% and 8.9% in routability in comparison with other work.

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