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Subject: search.filters.subject.kink effect

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Now showing 1 - 5 of 5
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    Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors
    (2000-07-01)
    Shih, PS
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    Zan, HW
    ;
    Chang, TC
    ;
    Huang, TY
    ;
    Chang, CY
    N-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.
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    A W-spacer GOLD TFT with high performance and high reliability
    (2002-09-26)
    Zan, HW
    ;
    Peng, DZ
    ;
    Shih, PS
    ;
    Chang, TC
    ;
    Liu, PT
    In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    Investigation of grain boundary control in the drain junction on laser-crystalized poly-Si thin film transistors
    (2003-07-01)
    Chen, TF
    ;
    Yeh, CF
    ;
    Lou, JC
    ;
    電子工程學系及電子研究所
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    Department of Electronics Engineering and Institute of Electronics
    This letter investigates the influences of grain boundaries in the drain junction on the performance and reliability of laser-crystalized poly-Si thin film transistors (TFTs). A unique test structure where the channel. region includes 150-nm-thick laser-crystalized poly-Si with, small grain sizes and a 100-nm-thick one with large grain sizes is fabricated. Different behaviors in the electrical characteristics and reliability of a single TFT are observed under measurements of the forward mode and then under first measurements of the reverse mode. This is due to the different number of, grain boundaries in the drain junction. Grain boundaries in the drain junction were found to cause reduced ON/OFF current ratio, variations in threshold voltage With drain bias, significantly, increased kink effect in the output characteristics, and poor hot-carrier stress endurance.
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    Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure
    (2004-09-01)
    Kuo, PY
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    Chao, TS
    ;
    Lei, TF
    ;
    電子工程學系及電子研究所
    ;
    奈米中心
    In this letter, we developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si thin-film transistors (TFTs). Experimental results,show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. The characteristics of the SSOB-TFTs are suitable for high-performance driving TFTs with a high output resistance and large breakdown voltage.
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    Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors
    (2011-11-01)
    Liao, Chia-Chun
    ;
    Lin, Min-Chen
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    Chiang, Tsung-Yu
    ;
    Chao, Tien-Sheng
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    電子物理學系
    SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes.