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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Subject: search.filters.subject.latchup

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Now showing 1 - 10 of 19
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    Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25-mu m 60-V/5-V BCD Technology
    (2017-08-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.
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    Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
    (2018-02-01)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The modified silicon-controlled rectifier (SCR) fabricated in a 0.25-mu m high-voltage (HV) bipolar-CMOS-DMOS (BCD) technology has been proposed to seek for both effective electrostatic discharge (ESD) protection and latchup immunity. Experimental results show that one of the proposed SCRs has a high holding voltage of up to similar to 30 V in the 100-ns transmission line pulsing measurement results. However, through the experimental verification by using the transient latchup test, the holding voltage of such proposed device decreases to similar to 20 V. It is due to the increased bipolar junction transistor current gains of the SCR path induced by the Joule-heating effect in the long-term measurement. For 20-V circuit applications, the ESD robustness of the proposed SCR with a holding voltage of similar to 20 V is lower than that of stacked low-voltage p-type MOS in the previous studies. Developing special modification of such HV devices is inefficient to achieve both effective ESD protection and latchup-free design in this 0.25-mu m HV BCD technology.
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    ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
    (2017-02)
    Ker, Ming-Dou
    ;
    Chiu, Po-Yen
    ;
    Shieh, Wuu-Trong
    ;
    Wang, Chun-Chi
    ;
    電子工程學系及電子研究所
    Due to the snapback holding voltage of high-voltage (HV) nMOS smaller than the maximum operating voltage, the traditional power-rail electrostatic discharge (ESD) clamp circuit implemented with such HV nMOS suffered latchup-like failure in a touch panel control IC after the system-level ESD test. A modified design on the power-rail ESD clamp circuit is proposed and verified in an HV CMOS process with 12 V double-diffused drain MOS device. With the holding voltage greater than the maximum operating voltage of 12 V, the touch panel equipped with the modified control IC can successfully pass the system-level ESD test of +/- 15 kV in the air-discharge test mode to meet the level 4 of IEC 61000-4-2 industry specification.
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    Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process
    (2016-06)
    Dai, Chia-Tsen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The optimization of guard ring structures to improve latchup immunity in an 18 V double-diffused drain MOS (DDDMOS) process with the DDDMOS transistors has together been investigated in a silicon test chip. The layout parameters including the anode-to-cathode spacing and the guard ring width are also studied to seek their impacts on latchup immunity. The measurement results demonstrated that the test devices isolated with the specific guard ring structure of n-buried layer can highly improve the latchup immunity. The suggested guard ring structures can be applied to the high-voltage circuits in this 18 V DDDMOS process to meet the new Joint Electron Device Engineering Council standard (JESD78D) with the trigger current of over +/- 200 mA.
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    Active Guard Ring to Improve Latch-Up Immunity
    (2014-12-01)
    Tsai, Hui-Wen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new design concept named as active guard ring and related circuit implementation to improve the latch-up immunity of ICs are proposed. Using additional sensing circuit and active buffer to turn ON the electrostatic discharge (ESD) protection transistors, the large-dimensional ESD (or I/O) devices can provide or receive extra compensation current to the negative or positive current perturbation during the latch-up current test. The new proposed solution has been verified in 0.6-mu m 5 V process to have much higher latch-up resistance compared with the conventional prevention method of guard ring in CMOS technology.
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    Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
    (2008-11-01)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mu m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
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    Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
    (2003-05-01)
    Ker, MD
    ;
    Lo, WY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances, A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. I Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-mum nonsilicided, a 0.35-mum silicided, and a 0.25-mum silicided shallow-trench-isolation bulk CMOS processes.
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    Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
    (2004-09-01)
    Ker, MD
    ;
    Lin, KH
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.
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    ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
    (2010-12-01)
    Wang, Chang-Tzu
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-mu m 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.
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    Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
    (2014-03-01)
    Tsai, Hui-Wen
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presented a practical industry case of electrical overstress (EOS) failure induced by the latchup test in high-voltage integrated circuits (ICs). By using proper layout modification and additional circuit, the unexpected EOS failure, which is caused by negative-current-triggered latchup test, can be successfully solved. The new design with proposed solutions has been verified in the 0.6-mu m 40-V Bipolar CMOS DMOS (BCD) process to pass the test for at least 500-mA trigger current, which shows high negative-current-latch-up immunity without overstress damage, compared with the protection of only the guard ring. Such solutions can be adopted to implement high-voltage-applicable IC product to meet the industry requirement for the mass production of IC manufactures and applications.