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Design and Simulation of High Performance Lattice Matched Double Barrier Normally Off AlInGaN/GaN HEMTs
(2020-01-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Chen, Chao-Hsuan
;
Sanyal, Indraneel
;
Tarng, Jenn-Hawn
A novel lattice matched double barrier Al0.72In0.16Ga0.12N/Al0.18In0.04Ga0.78N/GaN normally-off high electron mobility transistor (HEMT) is designed and simulated by solving a set of thermodynamic transport equations. Using the experimentally calibrated physical models with bearing mobility degradation by surface roughness in account, the recess gate and double barrier of the proposed device achieves a maximum drain current density (I-D,I-max) of 1149 mA/mm and a maximum transconductance (g(m,max)) of 358 mS/mm with a positive threshold voltage (Vth) of 0.2 V. The small polarization charge of first barrier is responsible for positive Vth. I-DS,I-max in the double barrier HEMT at high gate bias condition is due to injection of electrons from upper 2DEG which is almost impossible at lower gate voltage because of insufficient energy to cross the barrier. The injection of electrons is further supported by the second peak in the g(m) curve at low gate bias V-G = 1V. The outcome of this study suggests that the proposed device will be beneficial for high-frequency and high-power electronic applications.
SiC Strained nMOSFETs With Enhanced High- Frequency Performance and Impact on Flicker Noise and Random Telegraph Noise
(2020-06-01)
Guo, Jyh-Chyurn
;
Chang, Chih-Shiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Silicon-carbon (SiC) strained nMOSFETs with sub35-nm gate length in a 40-nm CMOS technology can realize superior cutoff frequency (f(T)) up to 405 GHz, attributed to more than 20% enhancement of the mobility and transconductance. This super-400-GHz f(T) makes SiC strained nMOS an attractive high mobility device aimed at millimeter-wave (mm-wave) CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase in flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants (tau(c) and tau(e)) and suggests electron-phonon coupling responsible for the anomalously slow trapping and detrapping, due to a significant increase of relaxation energy from SiC strain. This critical tradeoff between high-frequency performance and low-frequency noise becomes a key factor to be considered for the most appropriate adoption of high mobility devices and design optimization adapted to various circuits.
Electrical Characteristic of AlGaN/GaN High-Electron-Mobility Transistors With Recess Gate Structure
(2019-04-01)
Shrestha, Niraj Man
;
Li, Yiming
;
Suemitsu, Tetsuya
;
Samukawa, Seiji
;
交大名義發表
AlGaN/GaN high-electron-mobility transistors (HEMTs) with nonrecess and recess gates are simulated by solving a set of drift-diffusion equations for electrostatic potential and electron-hole concentrations with self-heating model. The approach is first calibrated for both HEMT devices with experimentally measured data, to provide the best accuracy of the simulation. Recess gate device suffers from high potential to the channel, increased parasitic resistances, and deep level traps in barrier due to surface roughness. In addition, selective thinning of the barrier and increase parasitic resistance results in 17% reduction on the carrier concentration. The carrier mobility degradation due to surface roughness and electron velocity lessen due to high electric field result shrinkage of current density with considerable shift of the threshold voltage toward positive value. Even though transconductance does not seems to be remarkably changed for 3-nm recess gate, its value increases on deeper recess. This paper reveals that surface roughness is crucial issue that has dominant role behind the low current density in the recess gate structure. The detail physical understanding of the recess technology will be helpful to minimize the performance deterioration of the explored devices.
A Model for Neutral Defect Limited Electron Mobility in Strained-Silicon Inversion Layers
(2017-03-01)
Hsieh, Shang-Hsun
;
Chen, Ming-Jer
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On the strained silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), we show how to derive a formalism dealing with the scattering of a 2-D electron by a neutral defect. The corresponding neutral defect limited inversion-layer electron mobility, mu(n), is calculated in the momentum relaxation time approximation. The calculated results lead to a new analytical model: mu(n) = cN(n)(-1) where N-n is the neutral defect density per unit area and c is the coefficient independent of the inversion-layer density, the strain, and the temperature. The validity and applicability of the model are confirmed by citing three independent experiments on strained silicon MOSFETs undergoing different implantation sources and different annealing budgets. Importantly, this paper clarifies for the first time that strain will not change neutral defect limited mobility unless changing the neutral defect density. This reasonably explains the two experimental observations during implantation and annealing: 1) the implantation-induced strain relaxation in strained sample does not occur and 2) the neutral defect density is much higher in strained sample than in unstrained sample.
Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride
(2005-04-01)
Lu, TY
;
Chao, TS
;
交大名義發表
;
National Chiao Tung University
A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G(M)) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G(M) of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G(M) further to 29% more than the single-poly-Si gate structure without SiN capping layer.
Modeling and Analysis of Channel Holding Time and Handoff Rate for Packet Sessions in All-IP Cellular Networks
(2017-04-01)
Ku, Bying-He
;
Ren, Yi
;
Weng, Jeng-Feng
;
Chen, Jyh-Cheng
;
Chen, Wen-Tsuen
It is essential to model channel holding time (CHT), cell residence time (CRT), and handoff rate for performance analysis and algorithm evaluation in mobile cellular networks. The problem has been extensively studied in the past for circuit-switched (CS) cellular networks. However, little research has been done on packet-switched (PS) cellular networks. Unlike that a call occupies a dedicated channel during its whole lifetime in CS networks, an active session in PS networks occupies and releases channels iteratively due to discontinuous reception (DRX) mechanism. In this paper, we investigate the key quantities in PS cellular networks. We present a set of comprehensive new models to characterize the quantities and their relationship in PS networks. The models shed light on the relationship between CHT and CRT and handoff rate. The analytical results enable wide applicability in various scenarios and therefore have important theoretical significance. Moreover, the analytical results provide a quick way to evaluate traffic performance and system design in PS cellular networks without wide deployment, which can save cost and time.
DC/AC/RF Characteristic Fluctuations Induced by Various Random Discrete Dopants of Gate-All-Around Silicon Nanowire n-MOSFETs
(2018-06-01)
Sung, Wen-Li
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal-oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage (Vth) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of Vth. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process.
Rational Design of ZnO:H/ZnO Bilayer Structure for High Performance Thin-Film Transistors
(2016-03-30)
Abliz, Ablat
;
Huang, Chun-Wei
;
Wang, Jingli
;
Xu, Lei
;
Liao, Lei
The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (similar to 3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V-1 s(-1), a high on/off current ratio of 108 and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.
High-Performance Submicrometer ZnON Thin-Film Transistors With Record Field-Effect Mobility
(2016-03)
Kuan, Chin-I
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this letter, we demonstrate 0.6-mu m ZnON thin-film transistors (TFTs) with the field-effect mobility of 71 cm(2)/V-sec, which to the best of our knowledge is the highest value ever reported on submicrometer oxide-semiconductor TFTs. The drive current, field-effect mobility, and subthreshold slope of ZnON TFTs are significantly improved as compared with their counterpart ZnO TFTs of the same channel dimensions and structure. Such an improvement in the field-effect mobility primarily results from a considerable reduction in the series source/drain (S/D) resistances because of suppression in an interfacial layer formation between Al S/D pads and the channel layer.
Channel Holding Time of Packet Sessions in All-IP Cellular Networks
(2014)
Weng, Jeng-Feng
;
Ku, Bying-He
;
Chen, Jyh-Cheng
;
Chen, Wen-Tsuen
;
資訊工程學系
In this paper, we analyze the packet session channel holding time for packet-switched cellular networks. Channel holding time depends on mobility which is characterized by cell residence time in this paper. We apply Hyper-Erlang distribution model to investigate the packet session channel holding time in which a session will experience active and idle periods. In terms of new session, handoff session in busy mode, handoff session with new arrival packets in idle mode and handoff session without arrival packet in idle mode, we demonstrate that the effective channel holding time is exponentially distributed if and only if the cell residence time is exponentially distributed. The analytical results provide a new approach to evaluate traffic performance and system design in packet-switched cellular networks.

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