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Subject: search.filters.subject.nonvolatile memory

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Now showing 1 - 10 of 54
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    Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations
    (2020-04-17)
    Lan, Yann-Wen
    ;
    Hong, Chuan-Jie
    ;
    Chen, Po-Chun
    ;
    Lin, Yun-Yan
    ;
    Yang, Chih-Hao
    A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.
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    A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
    (2020-01-01)
    You, Wei-Xiang
    ;
    Su, Pin
    ;
    Hu, Chenming
    ;
    電子工程學系及電子研究所
    ;
    國際半導體學院
    This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
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    Pulse-Driven Nonvolatile Perovskite Memory with Photovoltaic Read-Out Characteristics
    (2019-09-18)
    Chang, Shu-Jui
    ;
    Chen, Syuan-Ye
    ;
    Chen, Po-Wen
    ;
    Huang, Szu-Jung
    ;
    Tseng, Yuan-Chieh
    This paper presents a unique GdFe08Ni0.2O3 perovskite thin film for use in pulse-controlled nonvolatile memory devices (combined with a SrTiO3 (STO) substrate) without the need for an electrical-stressing read-out process. The use of pulse voltage imposes permanent downward/upward polarization states on GFNO, which enables greater energy density and higher energy efficiency than the unpoled state for memory. The two polarization states produce carrier migrations in opposing directions across the GFNO/STO interface, which alter the depletion region of the device, as reflected in photovoltaic short-circuit current density (J(sc)) values. Modulating the duration (varying the number of sequential pulses but fixing the pulse width and delay time) and direction of continuous pulse voltage is an effective method for controlling J(sc), thereby allowing the fabrication of nondestructive, light-tunable, nonvolatile memory devices. In experiments, J(sc) in the downward polarized state was approximately 6 times greater than that in the upward polarized state. It is promising that more memory states can be enabled by the proposed heterostructure by selecting appropriate pulse trains. Real-time interfacial changes (relative to the nonvolatile characteristics of the device) were obtained by applying synchrotron X-ray techniques simultaneously with pulse characterization. This made it possible to separately probe the electronic and chemical states of the GFNO (a p-type-like semiconductor) and STO (an n-type-like semiconductor) while varying the pulse direction, thereby making it possible to identify the mechanisms underlying the observed phenomena.
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    Ferroelectric Characterization of Hafnium-Oxide-Based Ferroelectric Memories with Remote Nitrogen Plasma Treatments
    (2019-01-01)
    Lee, You-Ting
    ;
    Chen, Hsuan-Han
    ;
    Tung, Yi-Chun
    ;
    Shih, Bing-Yang
    ;
    Hsiung, Szu-Yen
    In this paper, we experimentally demonstrated the advantage of remote nitrogen plasma on improving interface quality of HfO2-based ferroelectric devices. The remote nitrogen plasma not only reduces leakage current of gate stack to appropriately sustain the ferroelectricity during ferroelectric domain switching, but also effectively improve the ferroelectric fatigue to enhance endurance cycling performance.
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    Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String
    (2019-04-01)
    Lin, Wei-Liang
    ;
    Tsai, Wen-Jer
    ;
    Cheng, C. C.
    ;
    Ku, S. H.
    ;
    Liu, Lenvis
    Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 mu s or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in "pseudo" charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
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    Nitric Acid Oxidized ZrO2 as the Tunneling Oxide of Cobalt Silicide Nanocrystal Memory Devices
    (2011-09-01)
    Hu, Chih-Wei
    ;
    Chang, Ting-Chang
    ;
    Tu, Chun-Hao
    ;
    Chen, Yang-Dong
    ;
    Lin, Chao-Cheng
    In this study, ZrO2 formed by the nitric acid oxidation method is proposed to be the tunneling oxide for nonvolatile memory device applications. The sputtered Zr thin film was oxidized by immersing in the nitric acid solution (HNO3:H2O = 1:10) for 60 s at room temperature. The quality of the formed ZrO2 was also extracted by the capacitance-voltage and current density-voltage measurements. Then, X-ray photoelectron spectroscopy has been used to confirm that the deposited Zr can be oxidized completely after the oxidation process. Moreover, a CoSi2 thin film was deposited on the nitric acid oxidized ZrO2 as the self-assembled layer of the memory device. After the device fabrication, the electrical and material characteristics of the CoSi2 nanocrystal memory devices have also been demonstrated and discussed.
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    Low-Power and Highly Reliable Multilevel Operation in ZrO2 1T1R RRAM
    (2011-08-01)
    Wu, Ming-Chi
    ;
    Lin, Yi-Wei
    ;
    Jang, Wen-Yueh
    ;
    Lin, Chen-Hsi
    ;
    Tseng, Tseung-Yuen
    The Ti/ZrO2/Pt resistive memory devices with one transistor and one resistor (1T1R) architecture are successfully fabricated in this letter. The tested devices show low operation current (20 mu A), low switching voltage (set/reset, 0.8/-1 V), and reliable data retention for low-resistance state (LRS) with a 20-mu A set current at 80 degrees C (over ten years) via an excellent current limiter, namely, a metal-oxide-semiconductor field-effect transistor (MOSFET). In addition, multilevel storage characteristics are also demonstrated by modulating the amplitude of the MOSFET gate voltage. The various LRS levels obtained are possibly attributed to the formation of different numbers and sizes of conducting filaments consisting of oxygen vacancies caused by an external electric field. Moreover, reproducible resistive switching characteristics up to 2000 switching cycles are achieved in the same device. Our 1T1R ZrO2-based resistive switching access memory with low-power and highly reliable multilevel operation has high potential for practical applications.
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    Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement
    (2017-08-01)
    Chiu, Yu-Chien
    ;
    Cheng, Chun-Hu
    ;
    Liou, Guan-Lin
    ;
    Chang, Chun-Yen
    ;
    電子工程學系及電子研究所
    In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
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    In-Ga-O based double-heater phase change memory cell
    (2008)
    Wang, S. -L.
    ;
    Chen, C. -Y.
    ;
    Hsieh, M. -K.
    ;
    Lee, W. -C.
    ;
    Kung, A. H.
    We report a new type of phase-change materials based upon the compound of In-Ga-O. It is found to exhibit two-order of magnitude resistivity change between the high-resistive amorphous phase and the low-resistive cubic phase at a phase-change temperature similar to 250 degrees C. When the In-Ga-O is incorporated into a nonvolatile phase change memory (PCM) device with a double-heater (DH) structure, it exhibits an on/off resistance ratio of 1000 and cycling over 300 times which are superior to those observed on a single-heater (SH) PCM device. These results, together with a low bias point of 70 mu A at 6.5 volt and 1.5mA at 3.5 volt, respectively, for set/ reset operation of the DH-PCM device to the crystalline/amorphous state, suggest that In-Ga-O is a promising material candidate for low power application of PCM devices.
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    Impact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanisms
    (2015)
    Chiu, Yu-Chien
    ;
    Chang, Chun-Yen
    ;
    Hsu, Hsiao-Hsuan
    ;
    Cheng, Chun-Hu
    ;
    Lee, Min-Hung
    We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.