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具系統面板整合性之前瞻顯示電晶體元件製作與研究
(2008)
劉柏村
;
LIU PO-TSUN
;
國立交通大學光電工程學系(所)
本計畫將利用三年的時間來完成『高效能-具記憶體特性之多重奈米線薄膜電晶體』之製作與物理機制研究。近年來，主動式顯示面板技術蓬勃發展，為了提高面板的應用價值並降低製作成本，因此產業界期待發展出同時具有記憶體元件與驅動電路的系統整合型面板(system on panel; SOP)。由於複晶矽薄膜電晶體具有高的驅動電流，因此可取代外接式驅動電路整合於顯示面板中，以做為面板週邊的驅動元件。在本研究計畫中，將發展一種可應用於系統面板整合性的前瞻顯示元件技術，製作出能集畫素開關、驅動與記憶體特性於一身的高效能奈米線顯示電晶體，如此將可大大簡化系統面板技術中元件(即:驅動開關元件與記憶體元件)製程整合的複雜性，可使顯示面板同時具有驅動、讀取及儲存等功能，有效達到系統整合型面板之目的。在研究中，我們也將應用高介電常數薄膜於電晶體元件中，藉此提高顯示元件的記憶體功效與電晶體驅動特性；除此之外，我們將發展一種創新的薄膜缺陷鈍化技術，即：利用超臨界流體(supercritical fluid)技術，在低溫下對多晶矽薄膜電晶體元件內的缺陷進行鈍化(passivation)處理，可有效取代傳統高溫退火(annealing)及電漿(plasma)的製程，進一步提升顯示元件特性以及縮短製程時間與製造成本。最後，在計劃中也將對此高效能-具記憶體特性之顯示電晶體進行操作上的可靠性研究與物理機制探討，以瞭解實際應用於系統面板中可能遭遇到的問題。
具系統面板整合性之前瞻顯示電晶體元件製作與研究
(2009)
劉柏村
;
LIU PO-TSUN
;
國立交通大學光電工程學系(所)
本計畫將利用三年的時間來完成『高效能-具記憶體特性之多重奈米線薄膜電晶體』之製作與物理機制研究。近年來，主動式顯示面板技術蓬勃發展，為了提高面板的應用價值並降低製作成本，因此產業界期待發展出同時具有記憶體元件與驅動電路的系統整合型面板(system on panel; SOP)。由於複晶矽薄膜電晶體具有高的驅動電流，因此可取代外接式驅動電路整合於顯示面板中，以做為面板週邊的驅動元件。在本研究計畫中，將發展一種可應用於系統面板整合性的前瞻顯示元件技術，製作出能集畫素開關、驅動與記憶體特性於一身的高效能奈米線顯示電晶體，如此將可大大簡化系統面板技術中元件(即:驅動開關元件與記憶體元件)製程整合的複雜性，可使顯示面板同時具有驅動、讀取及儲存等功能，有效達到系統整合型面板之目的。在研究中，我們也將應用高介電常數薄膜於電晶體元件中，藉此提高顯示元件的記憶體功效與電晶體驅動特性；除此之外，我們將發展一種創新的薄膜缺陷鈍化技術，即：利用超臨界流體(supercritical fluid)技術，在低溫下對多晶矽薄膜電晶體元件內的缺陷進行鈍化(passivation)處理，可有效取代傳統高溫退火(annealing)及電漿(plasma)的製程，進一步提升顯示元件特性以及縮短製程時間與製造成本。最後，在計劃中也將對此高效能-具記憶體特性之顯示電晶體進行操作上的可靠性研究與物理機制探討，以瞭解實際應用於系統面板中可能遭遇到的問題。
具系統面板整合性之前瞻顯示電晶體元件製作與研究
(2007)
劉柏村
;
LIU PO-TSUN
;
國立交通大學光電工程學系(所)
本計畫將利用三年的時間來完成『高效能-具記憶體特性之多重奈米線薄膜電晶體』之製作與物理機制研究。近年來，主動式顯示面板技術蓬勃發展，為了提高面板的應用價值並降低製作成本，因此產業界期待發展出同時具有記憶體元件與驅動電路的系統整合型面板(system on panel; SOP)。由於複晶矽薄膜電晶體具有高的驅動電流，因此可取代外接式驅動電路整合於顯示面板中，以做為面板週邊的驅動元件。在本研究計畫中，將發展一種可應用於系統面板整合性的前瞻顯示元件技術，製作出能集畫素開關、驅動與記憶體特性於一身的高效能奈米線顯示電晶體，如此將可大大簡化系統面板技術中元件(即:驅動開關元件與記憶體元件)製程整合的複雜性，可使顯示面板同時具有驅動、讀取及儲存等功能，有效達到系統整合型面板之目的。在研究中，我們也將應用高介電常數薄膜於電晶體元件中，藉此提高顯示元件的記憶體功效與電晶體驅動特性；除此之外，我們將發展一種創新的薄膜缺陷鈍化技術，即：利用超臨界流體(supercritical fluid)技術，在低溫下對多晶矽薄膜電晶體元件內的缺陷進行鈍化(passivation)處理，可有效取代傳統高溫退火(annealing)及電漿(plasma)的製程，進一步提升顯示元件特性以及縮短製程時間與製造成本。最後，在計劃中也將對此高效能-具記憶體特性之顯示電晶體進行操作上的可靠性研究與物理機制探討，以瞭解實際應用於系統面板中可能遭遇到的問題。
Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
(1998-07-01)
Lee, YS
;
Lin, HY
;
Lei, TF
;
Huang, TY
;
Chang, TC
The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFT's
(1999-04-01)
Chen, HL
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Considering the impact-ionization mechanism occurring in the high drain-bias (V-DS) regime, a new I-V model considering the impact-ionization effect initiated by the drain-induced-grain-barrier-lowering (DIGBL) current has been established for the intrinsic n-channel poly-Si TFT, The simulation results with considering the developed impact-ionization current model are in excellent agreement with the experimental output characteristics of the intrinsic n-channel poly-Si TFT with the mask-gate length ranging from 5 mu m to 40 mu m. In resolving the physical parameters and their underlying operation mechanisms including the grain-barrier height, DIGBL current, and impact-ionization current, the developed I-V model will be beneficial to further understand the underlying physics of the intrinsic poky-Si TFT.
Dimensional effects on the drain current of n- and p-channel polycrystalline silicon thin film transistors
(2000-07-01)
Shih, PS
;
Zan, HW
;
Chang, TC
;
Huang, TY
;
Chang, CY
N-channcl and p-channel polysilicon thin him transistors (poly-Si TFTs) with different geometries were fabricated and characterized to study the interactive effects of active channel area on drain current. We find that for both non-passivated and passivated p-TFTs, since no avalanche multiplication is involved, the drain current is increased with reduced active channel area due to the reduction of grain-boundary trap density. In contrast, a somewhat unexpected trap dependence of the kink effect is observed in n-TFTs. Consequently, the dependence of active channel area on drain current differs between non-passivated n-TFTs with large trap density and passivated n-TFTs with small trap density.
Characterization and reliability of lightly-doped-drain polysilicon thin-film transistors with oxide sidewall spacer formed by one-step selective liquid phase deposition
(2000-10-01)
Shih, PS
;
Chang, TC
;
Huang, TY
;
Yeh, CF
;
Chang, CY
We have proposed and successfully demonstrated a novel process for fabricating a lightly doped drain (LDD) polysilicon thin-film transistor (poly-Si TFT). The oxide sidewall spacer in the new process is formed by a simple one-step selective liquid phase deposition (LPD) at 23 degreesC. In contrast with conventional methods, this new process does not require an additional photolithographic step for defining the non-self-aligned offset gate, or the deposition of an oxide layer and subsequent etch-back to form the: self-aligned sidewall spacer. Devices fabricated by the new process have a lower leakage current and a better ON/OFF current ratio, compared with non-LDD control devices. The new device also shows excellent current saturation characteristics at high bias and better has hot-carrier endurance. Since the apparatus used for LPD oxide deposition is simple and inexpensive, the new process appears to be promising for future high-performance poly-Si TFT fabrication.
Anomalous variations of OFF-state leakage current in poly-Si TFT under static stress
(2002-05-01)
Chang, KM
;
Chung, YH
;
Lin, GM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we study the anomalous variations of the OFF-state leakage current (I-OFF) in n-channel poly-Si thin-film transistors (TFTs) under static stress. The dominant mechanisms for the anomalous I-OFF can be attributed to 1) I-OFF increases due to channel hot electrons trapping at the gate oxide/channel interface and silicon grain boundaries and 2) I-OFF decreases due to hot holes accumulated/trapped near the channel/bottom oxide interface near the source region. Under the stress of high drain bias, serious impact ionization effect will occur to generate hot electrons and hot holes near the drain region. Some of holes will be injected into the gate oxide due to the vertical field (similar to(V_stress - V_ - Dstress) /T-ox) near the drain and the others will be migrated from drain to source along the channel due to lateral electric field (similar toV_Dstress/L-CH).
A W-spacer GOLD TFT with high performance and high reliability
(2002-09-26)
Zan, HW
;
Peng, DZ
;
Shih, PS
;
Chang, TC
;
Liu, PT
In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state. (C) 2002 Elsevier Science Ltd. All rights reserved.
A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain
(2003-08-01)
Zan, HW
;
Chang, TC
;
Shih, PS
;
Peng, DZ
;
Kuo, PY
With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.

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