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Subject: search.filters.subject.retention loss

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    Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
    (2011-04-01)
    Chou, Y. L.
    ;
    Chung, Y. T.
    ;
    Wang, Tahui
    ;
    Ku, S. H.
    ;
    Zou, N. K.
    Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.
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    奈米SONOS元件內單電子效應、可靠性物理及創新研究
    (2010)
    汪大暉
    ;
    WANG TAHUI
    ;
    國立交通大學電子工程學系及電子研究所
    非揮發性記憶體技術，隨著各種新式電子產品應用與龐大需求，已邁入100Gb 儲存之奈米世 代。在各種研發之非揮發性記憶體技術(例如, SONOS, PCM, RRAM,…)中，SONOS 已被公認為最 具可能取代傳統浮動閘極快閃式元件之下一世代記憶體技術。目前SONOS 元件已微縮至奈米尺 度, NOR-type SONOS 已微縮至50 奈米，二位元儲存，而NAND-type SONOS 已達42 奈米，隨著 技術繼續演進，無論在元件物理，元件結構與材料，新式操作方法及記憶體架構各方面，均將面 臨重大挑戰。本計劃將針對奈米SONOS 微縮時之新的物理機制與效應及創新方法，進行為期三 年之研究，內容將涵蓋基本元件理論，元件雜訊random telegraph noise(RTN)，單電子效應及其隨 機特性，蒙地卡羅電子傳輸模擬，及新式元件結構與記憶體架構。主要研究議題，敘述如下； 在 NOR-type SONOS 方面，由於採用熱電子寫入，以致於寫入時操作電壓無法低於3.5V 而 限制閘極長度之微縮。在本計劃，吾人將利用在奈米尺度電子呈現之非平衡傳輸現象，提出一種 新的熱電子操作方式，可將寫入時的操作電壓降至2.5V 以下。NOR-type SONOS 微縮時，另一物 理限制為熱電子寫入時，會經由二次電子(secondary hot electron)之產生而在鄰近元件造成干擾 (program disturb)，此種效應在bitline 微縮時，將愈益明顯，吾人將利用蒙地卡羅模擬研究此種機 制並試圖提出解決方法。此外，當元件微縮時，單一電子效應將更為顯著，單單一顆介面電荷 (interface charge)或儲存電荷(nitride charge)釋放即可能造成讀取錯誤，前者即為RTN，已被廣泛視 為40 奈米以下NAND Flash 之主要可靠性議題。而後者尚未有人報導，吾人將建立一量測技術， 以測量此種單電子效應，觀察其隨機性，並進行理論研究，藉由3D 數值模擬，建立此種單電子 效應之統計模型並決定採用error code correction 時所需位元數。吾人將探討此種單電子效應與元 件結構之關係，並提出一具有高度對稱性之元件結構，以降低此種單電子效應所造成讀取錯誤之 機率。
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    A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory
    (2011-03-01)
    Ma, Huan-Chi
    ;
    Chou, You-Liang
    ;
    Chiu, Jung-Piao
    ;
    Chung, Yueh-Ting
    ;
    Lin, Tung-Yang
    A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state V(t) retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10-20 program/erase cycles. Nitride charge vertical loss is verified by this method.