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Subject: search.filters.subject.substrate-triggered technique

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Now showing 1 - 10 of 11
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    Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
    (2002-05-01)
    Ker, MD
    ;
    Chen, TY
    ;
    Wu, CY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Ne electrostatic discharge (ESD) clamp devices for using in power-rail ESD clamp circuits with the substrate-triggered technique ire proposed to improve ESD level in a limited silicon area. The parasitic n-p-n and p-n-p bipolar junction transistors (BJTs) in the CMOS devices ire used to form the substrate-triggered devices Cor ESD protection. Four substrate-triggered de-ices are proposed and investigated in this work, which are named as the substrate-triggered lateral BJT, the substrate-triggered vertical BJT, the substrate-triggered double BJT and the double-triggered double BJT. An RC-based ESD-detection Circuit Is used to generate the triggering Current to turn on the proposed substrate-triggered devices. In order to trigger on the parasitic bipolar transistors more effectively, the symmetric multiple-cell square-type layout method is used to realize these substrate-triggered devices. The power-rail ESD clamp circuits, with such substrate-triggered devices have been fabricated in a 0.6-mum CMOS process. Experimental results have shown that the substrate-triggered device with double-BJT Structure can provide 200%, higher ESD robustness in per silicon area, as compared to the NMOS with the traditional gate-driven design, (C) 2002 Elsevier Science Ltd. All rights reserved.
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    Substrate-triggered ESD protection circuit without extra process modification
    (2003-02-01)
    Ker, MD
    ;
    Chen, TY
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole E.SD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 mum can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection,design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-mum salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V/mum(2) of ggnMOS to 1.73 V/mum(2).
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    Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
    (2003-02-01)
    Ker, MD
    ;
    Hsu, KC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the, base or - substrate of the SCR device, it can be quickly triggered, into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with, general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR, devices can be stacked in ESD protection circuits to avoid the translient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices, can be reduced from 27.4 to 7.8 ns by the substrate-triggering, technique. The substrate-triggered SCR device with a small active area of only 20 mum x 20 mum can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-mum CMOS process.
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    Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
    (2003-04-01)
    Ker, MD
    ;
    Chen, TY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The substrate triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as,comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits tor the input, output, and power pins have been designed and verified in a 0.18-mum salicided CMOS process. The experimental results have confirmed that the proposed substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices. The humari-body-model (HUM) ESD robustness of NMOS with a device dimension of W/L = 300 mum/0.3 mum can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV with the proposed substrate-triggered design.
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    Latchup-free ESD protection design with complementary substrate-triggered SCR devices
    (2003-08-01)
    Ker, MD
    ;
    Hsu, KC
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V-SS and pad-to-V-DD ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-mum salicided CMOS process with the human body model (machine model) ESD level of similar to7.25 kV (500 V) in a small layout area.
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    Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
    (2003-11-15)
    Ker, MD
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    Turn-on speed is the main concern for on-chip electrostatic discharge (ESD) protection device, especially, in deep submicron complementary metal-oxide semiconductors (CMOS) processes with ultra-thin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device with substrate-triggered technique is proposed to improve the turn-on speed of SCR device for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide. From the experimental results, the switching voltage, turn-on resistance, and turn-on time of substrate-triggered SCR (STSCR) device with dummy-gate structure have been efficiently improved, as compared with the normal SCR with shallow trench isolation (STI) structure.
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    On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
    (2004-10-01)
    Ker, MD
    ;
    Lin, KH
    ;
    Chuang, CH
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-mum salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.
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    ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
    (2005-01-01)
    Ker, MD
    ;
    Hsu, HC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A substrate-triggered technique is proposed to improve the electrostatic discharge (ESD) robustness of a stacked-nMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of a stacked-nMOS device to ensure effective ESD protection for mixed-voltage I/O circuits. The proposed ESD protection circuit with substrate- triggered design for a 2.5-V/3.3-V-tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-mum salicided CMOS process. The substrate-triggered circuit for a mixed-voltage I/O buffer to meet the desired circuit application in different CMOS processes can be easily adjusted by using HSPICE simulation. Experimental results have confirmed that the human-body-model (HBM) ESD robustness of a mixed-voltage I/O circuit can be increased similar to60% by this substrate-triggered design.
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    Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
    (2006-10-01)
    Ker, Ming-Dou
    ;
    Chen, Wen-Yi
    ;
    Hsu, Kuo-Chun
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.
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    Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
    (2009-03-01)
    Ker, Ming-Dou
    ;
    Wang, Chang-Tzu
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Two new electrostatic discharge (ESD) protection design by using only 1 x VDD low-voltage devices for mixed-voltage I/O buffer with 3 x VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13-mu m 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.