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Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
(2020-08-01)
Chiang, Hung-Li
;
Chen, Tzu-Chiang
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Song, Ming-Yuan
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Chen, Yu-Sheng
;
Chiu, Jung-Piao
To increase the density of magnetoresistive random accessmemory (MRAM) beyond the 1T1MTJMRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (V-TH-V-HOLD) when the selector is turned on. Also, exponential-type selectorswould degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Omega . mu m(2) and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density similar to 1 MA/cm(2)) and threshold-type selectors (V-TH-V-HOLD similar to 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
(2011-01-01)
Mukhopadhyay, Saibal
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Rao, Rahul M.
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Kim, Jae-Joon
;
Chuang, Ching-Te
;
交大名義發表
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.
Impact of Surface Orientation on the Sensitivity of FinFETs to Process Variations-An Assessment Based on the Analytical Solution of the Schrodinger Equation
(2010-12-01)
Wu, Yu-Sheng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the impact of surface orientation on V(th) sensitivity to process variations for Si and Ge fin-shaped field-effect transistors (FinFETs) using an analytical solution of the Schrodinger equation. Our theoretical model considers the parabolic potential well due to short-channel effects and, therefore, can be used to assess the quantum-confinement effect in short-channel FinFETs. Our study indicates that, for ultrascaled FinFETs, the importance of channel thickness (t(ch)) variations increases due to the quantum-confinement effect. The Si-(100) and Ge-(111) surfaces show lower V(th) sensitivity to the t(ch) variation as compared with other orientations. On the contrary, the quantum-confinement effect reduces the V(th) sensitivity to the L(eff) variation, and Si-(111) and Ge-(100) surfaces show lower V(th) sensitivity as compared with other orientations. Our study may provide insights for device design and circuit optimization using advanced FinFET technologies.
Statistical study on the temperature dependence of the turn-on characteristics for p-type LTPS TFTs
(2007-08-01)
Kuo, Yan-Fu
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Tai, Ya-Hsiang
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光電工程學系
;
顯示科技研究所
;
Department of Photonics
In recent years, low temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) has been widely investigated for various applications to system-on-panel (SOP) technology. However, due to the complexity of grain boundary trap properties, the conducting behaviors of various LTPS TFTs are difficult to be analyzed systematically. In this paper, the common and device-dependent thermal effects are studied to understand the conduction mechanism in the UPS TFTs. (c) 2007 Elsevier Ltd. All rights reserved.
A statistical model for simulating the effect of UPS TFT device variation for SOP applications
(2007-12-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Wan-Ping
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Chao, Yu-Te
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Chou, Yen-Pang
In this paper, the variation characteristics of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are investigated with a statistical approach. A special layout is proposed to investigate the device variation with respect to various devices distances. Two non-Gaussian equations are proposed to fit the device parameter distributions, whose the coefficients of determination (R(2)) are both near 0.9, reflecting the validity of the model. Two benchmark circuits are used to compare the difference between the proposed model and the conventional Gaussian distribution for the device parameter distribution. The output behaviors of the digital and analog circuits show that the variation in the short range would greatly affect the performance of the analog circuits and would instead be averaged in the digital circuits.
Multiple crack identification of a free-free beam with uniform material property variation and varied noised frequency
(2008-04-01)
Lin, Ren-Jeng
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Cheng, Fu-Ping
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土木工程學系
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Department of Civil Engineering
It is common to apply damage-sensitive features from vibration responses of a structure to assess structural damage. Few damage identification algorithms have focused on the material variation and measurement noise. For engineering practices, the material variation could be caused by many reasons and there always exists a certain level noise in measurement; those facts may affect the features that are used for structure monitoring and also lead to inaccurate assessment. In this research the authors have proposed a model to assess the statistical structural damage of a beam structure. The modal curvature-base feature was used to identify crack locations. The statistical damage databases were built by applying the Latin hypercube sampling method in Monte Carlo simulation. By mapping features of noised modal frequency to the statistical damage database, the damage probabilities among various crack depths were estimated; the statistical significance of damage level was examined by the t-test. Simulated beams and their experimental modal analysis data demonstrated the assessment procedures. The authors concluded that the proposed algorithm was robust and able to identify the damage of a free-free beam with uniform mass density and stiffness variations incorporated with noise in measured frequency. (C) 2007 Elsevier Ltd. All rights reserved.
Sensitivity of multigate MOSFETs to process variations - An assessment based on analytical solutions of 3-D Poisson's equation
(2008-05-01)
Wu, Yu-Sheng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the sensitivity of multigate MOSFETs to process variations using analytical solutions of 3-D Poisson's equation verified with device simulation. FinFET and Tri-gate with both heavily doped and lightly doped channels have been examined regarding their immunity to process-induced variations and dopant number fluctuation. Our study indicates that lightly doped FinFET has the smallest threshold voltage (V-th) dispersion caused by process variations and dopant number fluctuation. For heavily doped devices, dopant number fluctuation may become the dominant factor in the determination of overall V-th variation. The V-th dispersion of Tri-gate may therefore be smaller than that of FinFET because of its better immunity to dopant number fluctuation.
Characterization of poly-Si TFT variation using interdigitated method
(2008-08-01)
Huang, Shih-Che
;
Tai, Ya-Hsiang
;
光電工程學系
;
顯示科技研究所
;
Department of Photonics
In this paper, the device variation characteristic of poly-Si TFTs is statistically investigated. First the variation of devices is examined with respect to different device distance. It is found that the device variation would exhibit similar behavior for different device distance. Then, in order to study the method to suppress device variation, the interdigitated layout is adopted. It is found that though the variation behavior of the poly-Si TFTs is much more serious and complicated than MOSFETs, the law of area can still be utilized to describe the variation behavior in the interdigitated layout. The fitting parameters in law of area can provide insights for understanding the intrinsic variation behavior for poly-Si TFTs and the discussion about the variation for the device with various channel width is provided. The variation behavior of poly-Si TFTs is then compared with amorphous silicon TFTs and single crystal silicon MOSFETs. The impacts of poly-Si TFT variation on circuit design and performance is also discussed. (C) 2008 Elsevier Ltd. All rights reserved.
Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations
(2008-11-01)
Hsu, Hsing-Hui
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Liu, Ta-Wei
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Chan, Leng
;
Lin, Chuan-Ding
;
Huang, Tiao-Yuan
Several types of poly-Si nanowire (NW) thin-film transistors (TFTs) with multiple-gated (MG) configuration were demonstrated and characterized. These devices were fabricated with simple methods without resorting to costly lithographic tools and processes. The fabricated trigated devices show a low subthreshold swing (SS) of around 100 mV/dec and on/off current ratio higher than 10(8). These results clearly indicate the effectiveness of MG scheme in enhancing the device performance. Furthermore, a multiple-channel scheme was demonstrated to further increase the drive current without compromising device performance. Finally, the impact of MG on the variation of NWTFT characteristics is investigated with a clever method that allows the fabrication of test structures with identical NW channel but different gate configurations. The results,clearly show that the variation could be reduced by increasing the portion of NW channel surface that is modulated by the gate.
Sensitivity of Gate-All-Around Nanowire MOSFETs to Process Variations-A Comparison With Multigate MOSFETs
(2008-11-01)
Wu, Yu-Sheng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the sensitivity of gate-all-around (GAA) nanowire (NW) to process variations compared with multigate devices using analytical solutions of Poisson's equation verified with device simulation. GAA NW and multigate devices with both heavily doped and lightly doped channels have been examined regarding their immunity to process-induced variations and dopant number fluctuation. Our study indicates that the lightly doped GAA NW has the smallest threshold voltage (V-th) dispersion caused by process variations and dopant number fluctuation. Specifically, the GAA NW shows better immunity to channel thickness variation than multigate devices because of its inherently superior surrounding gate structure. For heavily doped devices, dopant number fluctuation may become the dominant factor in the determination of overall V-th variation. The V-th dispersion of GAA NW may therefore be larger than that of multigate MOSFETs because of its larger surface-to-volume ratio.

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