标题: | 奈米SONOS元件内单电子效应、可靠性物理及创新研究 Single Charge Phenomena, Scaling Physical Mechanisms and Innovations in Nano-Scale Sonos Flash Memory |
作者: | 汪大晖 WANG TAHUI 国立交通大学电子工程学系及电子研究所 |
关键字: | 单一储存电子;SONOS快闪式记忆体;保留电子流失;蒙地卡罗模拟;single program charge;SONOS;percolation;retention loss;Monte Carlo simulation |
公开日期: | 2010 |
摘要: | 非挥发性记忆体技术,随着各种新式电子产品应用与庞大需求,已迈入100Gb 储存之奈米世 代。在各种研发之非挥发性记忆体技术(例如, SONOS, PCM, RRAM,…)中,SONOS 已被公认为最 具可能取代传统浮动闸极快闪式元件之下一世代记忆体技术。目前SONOS 元件已微缩至奈米尺 度, NOR-type SONOS 已微缩至50 奈米,二位元储存,而NAND-type SONOS 已达42 奈米,随着 技术继续演进,无論在元件物理,元件结构与材料,新式操作方法及记忆体架构各方面,均将面 臨重大挑战。本计划将针对奈米SONOS 微缩时之新的物理机制与效应及创新方法,进行为期三 年之研究,内容将涵盖基本元件理論,元件杂讯random telegraph noise(RTN),单电子效应及其随 机特性,蒙地卡羅电子传输模拟,及新式元件结构与记忆体架构。主要研究议题,叙述如下; 在 NOR-type SONOS 方面,由于采用热电子写入,以致于写入时操作电压无法低于3.5V 而 限制闸极长度之微缩。在本计划,吾人将利用在奈米尺度电子呈现之非平衡传输现象,提出一种 新的热电子操作方式,可将写入时的操作电压降至2.5V 以下。NOR-type SONOS 微缩时,另一物 理限制为热电子写入时,会经由二次电子(secondary hot electron)之产生而在邻近元件造成干扰 (program disturb),此种效应在bitline 微缩时,将愈益明显,吾人将利用蒙地卡羅模拟研究此种机 制并试图提出解决方法。此外,当元件微缩时,单一电子效应将更为显着,单单一颗介面电荷 (interface charge)或储存电荷(nitride charge)释放即可能造成讀取错误,前者即为RTN,已被广泛视 为40 奈米以下NAND Flash 之主要可靠性议题。而后者尚未有人报导,吾人将建立一量测技术, 以测量此种单电子效应,观察其随机性,并进行理論研究,藉由3D 數值模拟,建立此种单电子 效应之统计模型并决定采用error code correction 时所需位元數。吾人将探讨此种单电子效应与元 件结构之关系,并提出一具有高度对称性之元件结构,以降低此种单电子效应所造成讀取错误之 机率。 As non-volatile memory (NVM) is moving rapidly into 100 Gb era, conventional floating gate flash memory suffers from serious coupling issues between cells, thus limiting its further scaling beyond 30nm. Among various alternative NVM technologies (SONOS, PCM, RRAM, ..), SONOS flash is generally considered to be the most promising technology for next-generation NVM. Currently, the SONOS technology node is 50nm for 2-bit storage NOR Flash and 42nm for NAND Flash. As the technology further advances, considerable challenges in cell operation principle, cell structures, materials and reliability physics will be encountered. This project will explore new phenomena, limiting physical mechanisms and innovations of the SONOS technology in scaling. The scope of this research includes single charge phenomena and stochastic process, random telegraph noise (RTN) characterization and 3D simulation, non-equilibrium transport and Monte Carlo simulation, new cell structures and operational principle. Major research topics are described below. For NOR-type SONOS by using hot electron programming, a large drain-to-source voltage Vds (~3.5V) is required for electrons to surmount the SiO2/Si barrier (i.e., 3.1eV). As gate length is reduced, channel punch-through caused by a large Vds becomes a limiting constraint in SONOS scaling. To make a breakthrough, we propose a new hot electron programming method by taking advantage of electron non-equilibrium transport in nano-meter scale devices. In our method, program Vds can be reduced to 2.5V. Besides, we observe a new hot electron program disturb in bit-line scaling, which is attributed to impact ionization-generated secondary hot electrons during programming. A multi-step Monte Carlo simulation will be performed to explore the disturb mechanism. New cell structures to alleviate the disturb will be investigated. In addition, single charge effects are becoming more prominent as devices are further scaled. A single interface (oxide) charge emission or a single program (nitride) charge loss may induce a large fluctuation in read current and cause a read failure. The former has been recognized as random telegraph noise and has been widely accepted as a major failure mechanism in flash memory beyond 40 nm node. The latter has not been published yet. In this project, we will establish a measurement method based on our paper at 2005 VLSI Symp. on Tech. (Best Student Paper Award) to characterize individual program charge retention times, their locations and corresponding changes in read current. We will perform 3D simulation to study current-path percolation effect and develop a statistical model for the retention Vt distribution. New SONOS cells with higher degree of symmetry in programmed charge distributions, for example, (nano-wire SONOS or rounded-corner FinFET SONOS) will be studied, which is expected to have reduced single charge effects (i.e., smaller RTN and Vt loss tail). |
官方说明文件#: | NSC99-2221-E009-171-MY3 |
URI: | http://hdl.handle.net/11536/100475 https://www.grb.gov.tw/search/planDetail?id=2114892&docId=338099 |
显示于类别: | Research Plans |